Abstract: Provided is a method for increasing pattern density of a structure on a substrate using an integration scheme, the method comprising: providing a substrate having a first spacer pattern and an underlying layer, the underlying layer comprising a first underlying layer, a second underlying layer, and a target layer; performing a conformal spacer deposition using an oxide, the deposition creating a conformal layer; performing a spacer RIE process and a pull process, thereby generating a second spacer pattern, the spacer RIE process includes adsorption of N-containing gas on a surface of the substrate which activates the surface to react with an F- and/or an H-containing gas to form fluorosilicates; and wherein the integration targets include selectively etching spacer films within a target spacer etch rate, enhanced simultaneous selectivity to the first underlying layer and the second underlying layer and preventing pattern damage.

Abstract: Techniques herein provide methods for depositing spin-on metal materials for creating metal hard mask (MHM) structures without voids in the deposition. This includes effective spin-on deposition of TiOx, ZrOx, SnOx, HFOx, TaOx, et cetera. Such materials can help to provide differentiation of material etch resistivity for differentiation. By enabling spin-on metal hard mask (MHM) for use with a multi-line layer, a slit-based or self-aligned blocking strategy can be effectively used. Techniques herein include identifying a fill material to fill particular openings in a given relief pattern, modifying a surface energy value of surfaces within the opening such that a contact angle value of an interface between the fill material in liquid form and the sidewall or floor surfaces enables gap-free or void-free filling.

Abstract: Techniques herein provide a process to reform or flatten asymmetric spacers to form a square profile which creates symmetric spacers for accurate pattern transfer. Initial spacer formation typically results in spacer profiles with a curved or sloped top surfaces. This asymmetric top surface is isolated while protecting a remaining lower portion of the spacer. The top surface is removed using a plasma processing step resulting in spacers having a squared profile that enables further patterning and/or accurate pattern transfer.

Abstract: Provided is a method for increasing pattern density of a structure on a substrate using an integration scheme, the method comprising: providing a substrate having a first spacer pattern and an underlying layer, the underlying layer comprising a first underlying layer, a second underlying layer, and a target layer; performing a second conformal spacer deposition using an oxide, the deposition creating a second conformal layer; performing a second spacer RIE process and a second pull process, wherein generating a second spacer pattern, the second spacer RIE process includes adsorption of N containing gas on a surface of the substrate which activates the surface to react with an F and/or an H-containing gas to form fluorosilicates; and wherein the integration targets include selectively etching spacer films within a target spacer etch rate, enhanced simultaneous selectivity to the first underlying layer and the second underlying layer and preventing pattern damage.

Abstract: A method and system for the dry removal of a material on a microelectronic workpiece are described. The method includes receiving a workpiece having a surface exposing a target layer to be at least partially removed, placing the workpiece on a workpiece holder in a dry, non-plasma etch chamber, and selectively removing at least a portion of the target layer from the workpiece. The selective removal includes operating the dry, non-plasma etch chamber to perform the following: exposing the surface of the workpiece to a chemical environment at a first setpoint temperature in the range of 35 degrees C. to 100 degrees C. to chemically alter a surface region of the target layer, and then, elevating the temperature of the workpiece to a second setpoint temperature at or above 100 degrees C. to remove the chemically treated surface region of the target layer.

Abstract: A method for the dry removal of a material on a microelectronic workpiece is described. The method includes receiving a workpiece having a surface exposing a target layer composed of silicon and either (1) organic material or (2) both oxygen and nitrogen, and selectively removing at least a portion of the target layer from the workpiece. The selective removal includes exposing the surface of the workpiece to a chemical environment containing N, H, and F at a first setpoint temperature to chemically alter a surface region of the target layer, and then, elevating the temperature of the workpiece to a second setpoint temperature to remove the chemically treated surface region of the target layer.

Abstract: Techniques herein include methods for curing a layer of material (such as a resist) on a substrate to enable relatively greater heat reflow resistance. Increasing reflow resistance enables successful directed self-assembly of block copolymers. Techniques include receiving a substrate having a patterned photoresist layer and positioning this substrate in a processing chamber of a capacitively coupled plasma system. The patterned photoresist layer is treated with a flux of electrons by coupling negative polarity direct current power to a top electrode of the plasma processing system during plasma processing. The flux of electrons is accelerated from the top electrode with sufficient energy to pass through a plasma and its sheath, and strike the substrate such that the patterned photoresist layer changes in physical properties, which can include an increased glass-liquid transition temperature.

Abstract: Provided is a method for patterning a substrate, comprising: forming a layer of radiation-sensitive material on a substrate; preparing a pattern in the layer of radiation-sensitive material using a lithographic process, the pattern being characterized by a critical dimension (CD) and a roughness; following the preparing the pattern, performing a CD shrink process to reduce the CD to a reduced CD; and performing a growth process to grow the reduced CD to a target CD. Roughness includes a line edge roughness (LER), a line width roughness (LWR), or both LER and LWR. Performing the CD shrink process comprises: coating the pattern with a hard mask, the coating generating a hard mask coated resist; baking the hard mask coated resist in a temperature range for a time period, the baking generating a baked coated resist; and developing the baked coated resist in deionized water.

Abstract: Techniques herein include methods of processing photoresist patterns and photoresist materials for successful use in multi-patterning operations. Techniques include combinations of targeted deposition, curing, and trimming to provide a post-processed resist that effectively enables multi-patterning using photoresist materials to function as mandrels. Photoresist patterns and mandrels are hardened, strengthened, and/or dimensionally adjusted to provide desired dimensions and/or mandrels enabling straight sidewall spacers. Polymer is deposited with tapered profile to compensate for compressive stresses of various conformal or subsequent films to result in a vertical profile despite any compression.

Abstract: Techniques disclosed herein include methods for DSA patterning and curing of DSA patterns. Techniques include curing phase-separated block copolymers using vacuum ultraviolet (VUV) light exposure at wavelengths from about 100 nanometers to 170 nanometers. VUV light can be generated using a plasma process system and from energizing various VUV-generating process gasses. A VUV curing step is executed (fully or partially) prior to executing an etch process to etch away one of the block copolymers. Such VUV exposure can selectively harden one block copolymer while weakening another block copolymer. This hardening and weakening increases etch selectivity enabling more effective etching and results in better patterns.

Abstract: Provided is a method for increasing pattern density of a structure using an integration scheme and perform pitch splitting at the resist level without the use of hard mandrels, the method comprising: providing a substrate having a patterned resist layer and an underlying layer comprising a silicon anti-reflective coating layer, an amorphous layer, and a target layer; performing a resist hardening process; performing a first conformal spacer deposition using an atomic layer deposition technique with an oxide, performing a spacer first reactive ion etch process and a first pull process on the first conformal layer, performing a second conformal spacer deposition using titanium oxide; performing a second spacer RIE process and a second pull process, generating a second spacer pattern; and transferring the second spacer pattern into the target layer, wherein targets include patterning uniformity, pulldown of structures, slimming of structures, aspect ratio of structures, and line width roughness.

Abstract: Graphene particulates, especially graphene nanoribbons (GNRs) and graphene quantum dots (GQDs), and a high-throughput process for the production of such particulates is provided. The graphene particulates are produced by a nanotomy process in which graphene blocks are cut from a source of graphite and then exfoliated into a plurality of graphene particulates. Graphene particulates having narrow widths, on the order of 100 nm or less, can be produced having band gap properties suitable for use in a variety of electrical applications.

Abstract: Techniques disclosed herein include methods for DSA patterning and curing of DSA patterns. Techniques include curing phase-separated block copolymers using vacuum ultraviolet (VUV) light exposure at wavelengths from about 100 nanometers to 170 nanometers. VUV light can be generated using a plasma process system and from energizing various VUV-generating process gasses. A VUV curing step is executed (fully or partially) prior to executing an etch process to etch away one of the block copolymers. Such VUV exposure can selectively harden one block copolymer while weakening another block copolymer. This hardening and weakening increases etch selectivity enabling more effective etching and results in better patterns.

Abstract: The disclosure relates to methods for a multi-step plasma process to remove metal hard mask layer from an underlying hard mask layer that may be used to implement a sub-lithographic integration scheme. The sub-lithographic integration scheme may include iteratively patterning several features into the metal hard mask layer that may be transferred to the hard mask layer. However, the iterative process may leave remnants of previous films on top of the metal hard mask that may act as mini-masks that may interfere with the pattern transfer to the hard mask layer. One approach to remove the mini-masks may be to use a two-step plasma process that removes the mini-mask using a first gas mixture ratio of a carbon-containing gas and a chlorine-containing gas. The remaining metal hard mask layer may be removed using a second gas mixture ratio of the carbon-containing gas and the chlorine-containing gas.

Abstract: Techniques herein include methods for curing a layer of material (such as a resist) on a substrate to enable relatively greater heat reflow resistance. Increasing reflow resistance enables successful directed self-assembly of block copolymers. Techniques include receiving a substrate having a patterned photoresist layer and positioning this substrate in a processing chamber of a capacitively coupled plasma system. The patterned photoresist layer is treated with a flux of electrons by coupling negative polarity direct current power to a top electrode of the plasma processing system during plasma processing. The flux of electrons is accelerated from the top electrode with sufficient energy to pass through a plasma and its sheath, and strike the substrate such that the patterned photoresist layer changes in physical properties, which can include an increased glass-liquid transition temperature.

Abstract: Graphene particulates, especially graphene nanoribbons (GNRs) and graphene quantum dots Ds and and a high-throughput process for the production of such particulates is provided. The graphene particulates are produced by a nanotomy process in which graphene blocks are cut from a source of graphite and then exfoliated into a plurality of graphene particulates. Graphene particulates having narrow widths, on the order of 100 nm or less, can be produced having band gap properties suitable for use in a variety of electrical applications.