Abstract: There are disclosed herein various implementations of an insulated gate bipolar transistor (IGBT) with buried emitter electrodes. Such an IGBT may include a collector at a bottom surface of a semiconductor substrate, a drift region having a first conductivity type situated over the collector, and a base layer having a second conductivity type opposite the first conductivity type situated over the drift region. In addition, such an IGBT may include deep insulated trenches extending from a semiconductor surface above the base layer, into the drift region, each of the deep insulated trenches having a buried emitter electrode disposed therein. The IGBT may further include an active cell including an emitter, a gate trench with a gate electrode disposed therein, and an implant zone situated, between adjacent deep insulated trenches. The implant zone is formed below the base layer and has the first conductivity type.

Abstract: According to an exemplary implementation, a level shifter includes a low voltage circuit and a high voltage circuit. The low voltage circuit is configured to provide a differential signal to the high voltage circuit. The high voltage circuit is configured to receive the differential signal from the low voltage circuit so as to level shift the differential signal from a first ground of the low voltage circuit to a second ground of the high voltage circuit. The differential signal is provided by the low voltage circuit responsive to a feedback signal from the high voltage circuit. The feedback signal can indicate common mode noise in the level shifter. Furthermore, the low voltage circuit can be configured to refresh the differential signal responsive to the feedback signal.

Abstract: According to an exemplary implementation, a level shifter includes a low voltage circuit and a high voltage circuit. The low voltage circuit is configured to provide a differential signal to the high voltage circuit through a capacitive isolation barrier. The high voltage circuit is configured to receive the differential signal from the low voltage circuit through the capacitive isolation barrier so as to level shift the differential signal from a first ground of the low voltage circuit to a second ground of the high voltage circuit. The high voltage circuit is further configured to provide a feedback signal to the low voltage circuit through the capacitive isolation barrier. The low voltage circuit can be configured to receive the feedback signal from the low voltage circuit between edges of the differential signal.

Abstract: Disclosed is a power semiconductor device that includes a plurality of source trenches and adjacent source regions. The plurality of source trenches extend from a top surface of a semiconductor substrate into the semiconductor substrate. The power semiconductor device further includes a plurality of gate trenches that extend from the top of the semiconductor substrate into the semiconductor substrate, and are arranged in hexagonal or zigzag patterns. A contiguous formation is created by the plurality of gate trenches, and the plurality of gate trenches separate the plurality of source trenches from one another.

Abstract: According to an exemplary implementation, a level shifter includes a low voltage circuit and a high voltage circuit. The low voltage circuit is configured to provide a differential signal to the high voltage circuit through a capacitive isolation barrier. The high voltage circuit is configured to receive the differential signal from the low voltage circuit through the capacitive isolation barrier so as to level shift the differential signal from a first ground of the low voltage circuit to a second ground of the high voltage circuit. The high voltage circuit is further configured to provide a feedback signal to the low voltage circuit through the capacitive isolation barrier. The low voltage circuit can be configured to receive the feedback signal from the low voltage circuit between edges of the differential signal.

Abstract: One exemplary disclosed embodiment comprises a semiconductor package including a vertical conduction control transistor and a vertical conduction sync transistor. The vertical conduction control transistor may include a control source, a control gate, and a control drain that are all accessible from a bottom surface, thereby enabling electrical and direct surface mounting to a support surface. The vertical conduction sync transistor may include a sync drain on a top surface, which may be connected to a conductive clip that is coupled to the support surface. The conductive clip may also be thermally coupled to the control transistor. Accordingly, all terminals of the transistors are readily accessible through the support surface, and a power circuit, such as a buck converter power phase, may be implemented through traces of the support surface. Optionally, a driver IC may be integrated into the package, and a heatsink may be attached to the conductive clip.

Abstract: One exemplary disclosed embodiment comprises a semiconductor package including a vertical conduction control transistor and a vertical conduction sync transistor. The vertical conduction control transistor may include a control source, a control gate, and a control drain that are all accessible from a bottom surface, thereby enabling electrical and direct surface mounting to a support surface. The vertical conduction sync transistor may include a sync drain on a top surface, which may be connected to a conductive clip that is coupled to the support surface. The conductive clip may also be thermally coupled to the control transistor. Accordingly, all terminals of the transistors are readily accessible through the support surface, and a power circuit, such as a buck converter power phase, may be implemented through traces of the support surface. Optionally, a driver IC may be integrated into the package, and a heatsink may be attached to the conductive clip.

Abstract: According to an exemplary implementation, a level shifter includes a low voltage circuit and a high voltage circuit. The low voltage circuit is configured to provide a differential signal to the high voltage circuit. The high voltage circuit is configured to receive the differential signal from the low voltage circuit so as to level shift the differential signal from a first ground of the low voltage circuit to a second ground of the high voltage circuit. The differential signal is provided by the low voltage circuit responsive to a feedback signal from the high voltage circuit. The feedback signal can indicate common mode noise in the level shifter. Furthermore, the low voltage circuit can be configured to refresh the differential signal responsive to the feedback signal.

Abstract: According to an exemplary implementation, a level shifter includes a low voltage circuit and a high voltage circuit. The low voltage circuit is configured to provide a differential signal to the high voltage circuit through a capacitive isolation barrier. The high voltage circuit is configured to receive the differential signal from the low voltage circuit through the capacitive isolation barrier so as to level shift the differential signal from a first ground of the low voltage circuit to a second ground of the high voltage circuit. The high voltage circuit is further configured to provide a feedback signal to the low voltage circuit through the capacitive isolation barrier. The low voltage circuit can be configured to receive the feedback signal from the low voltage circuit between edges of the differential signal.

Abstract: According to an exemplary implementation, a field-effect transistor (FET) includes first and second gate trenches extending to a drift region of a first conductivity type. The FET also includes a base region of a second conductivity type that is situated between the first and second gate trenches. A ruggedness enhancement region is situated between the first and second gate trenches, where the ruggedness enhancement region is configured to provide an enhanced avalanche current path from a drain region to the base region when the FET is in an avalanche condition. The enhanced avalanche current path is away from the first and second gate trenches. The ruggedness enhancement region can be of the second conductivity type that includes a higher dopant concentration than the base region. Furthermore, the ruggedness enhancement region can be extending below the first and second gate trenches.

Abstract: There are disclosed herein various implementations of an insulated gate bipolar transistor (IGBT) with buried emitter electrodes. Such an IGBT may include a collector at a bottom surface of a semiconductor substrate, a drift region having a first conductivity type situated over the collector, and a base layer having a second conductivity type opposite the first conductivity type situated over the drift region. In addition, such an IGBT may include deep insulated trenches extending from a semiconductor surface above the base layer, into the drift region, each of the deep insulated trenches having a buried emitter electrode disposed therein. The IGBT may further include an active cell including an emitter, a gate trench with a gate electrode disposed therein, and an implant zone situated, between adjacent deep insulated trenches. The implant zone is formed below the base layer and has the first conductivity type.

Abstract: There are disclosed herein various implementations of an insulated-gate bipolar transistor (IGBT) with buried depletion electrode. Such an IGBT may include a collector at a bottom surface of a semiconductor substrate, a drift region having a first conductivity type situated over the collector, and a base layer having a second conductivity type opposite the first conductivity type situated over the drift region. The IGBT also includes a plurality of deep insulated trenches with a buried depletion electrode and at least one gate electrode disposed therein. In addition, the IGBT includes an active cell including an emitter adjacent the gate electrode, and an implant zone, situated between adjacent deep insulated trenches. The implant zone is formed below the base layer and has the first conductivity type. In one implementation, the IGBT may also include a dummy cell neighboring the active cell.

Abstract: A semiconductor device which includes a passivation structure formed with a conductive strip of resistive material that crosses itself once around the active region of the device to form a first closed loop, a continuous strip that loops around the first closed loop without crossing itself which crosses itself a second time to form a second closed loop.

Abstract: Disclosed is a method for fabricating a shallow and narrow trench field-effect transistor (trench FET). The method includes forming a trench within a semiconductor substrate of a first conductivity type, the trench including sidewalls and a bottom portion. The method further includes forming a substantially uniform gate dielectric in the trench, and forming a gate electrode within said trench and over said gate dielectric. The method also includes doping the semiconductor substrate to form a channel region of a second conductivity type after forming the trench. In one embodiment, the doping step is performed after forming the gate dielectric and after forming the gate electrode. In another embodiment, the doping step is performed after forming the gate dielectric, but prior to forming the gate electrode. Structures formed by the invention's method are also disclosed.

Abstract: A semiconductor device which includes a passivation structure formed with a conductive strip of resistive material that crosses itself once around the active region of the device to form a first closed loop, a continuous strip that loops around the first closed loop without crossing itself which crosses itself a second time to form a second closed loop.

Abstract: A semiconductor device which includes a passivation structure formed with a conductive strip of resistive material that crosses itself once around the active region of the device to form a first closed loop, a continuous strip that loops around the first closed loop without crossing itself which crosses itself a second time to form a second closed loop.

Abstract: A semiconductor device which includes a passivation structure formed with a conductive strip of resistive material that crosses itself once around the active region of the device to form a first closed loop, a continuous strip that loops around the first closed loop without crossing itself which crosses itself a second time to form a second closed loop.

Abstract: A high side driver chip for MOSgated devices which controls a non resistive, or non inductive load has a vertical conduction refresh MOSFET integrated into the chip for connecting a Vs node to ground to discharge the load capacitance. A Schottky diode is also integrated with the refresh MOSFET to prevent forward conduction of a parasitic diode of the vertical conduction MOSFET.

Abstract: A high side driver chip for MOSgated devices which controls a non resistive, or non inductive load has a vertical conduction refresh MOSFET integrated into the chip for connecting a Vs node to ground to discharge the load capacitance. A Schottky diode is also integrated with the refresh MOSFET to prevent forward conduction of a parasitic diode of the vertical conduction MOSFET.

Abstract: A high side driver chip for MOSgated devices which controls a non resistive, or non inductive load has a vertical conduction refresh MOSFET integrated into the chip for connecting a Vs node to ground to discharge the load capacitance. A Schottky diode is also integrated with the refresh MOSFET to prevent forward conduction of a parasitic diode of the vertical conduction MOSFET.