Abstract: A high voltage radiation hardened power integrated circuit (PIC) with resistance to TID and SEE radiation effects for application in high radiation environments, such as outer space. TID hardness modification include forming gate oxide layers after high temperature junction processes, adding implant layers to raise the parasitic MOSFET thresholds with respect to native thresholds, and suppressing CMOS drain-to-source and intrawell transistor-to-transistor leakage. In addition, radhard field oxide is utilized. SEE ruggedness is improved by reducing the epi thickness over that of non-radhard devices, and increasing the epi concentration near the substrate junction. A radhard PIC rated to 400 V and capable of operating at 600 V or more is provided. The inventive PIC can withstand 100 krads of TID and a heavy ion Linear Energy Transfer of 37 MeV/(mg/cm2) at full rated voltage.

Abstract: A high voltage radiation hardened power integrated circuit (PIC) with resistance to TID and SEE radiation effects for application in high radiation environments, such as outer space. TID hardness modification include forming gate oxide layers after high temperature junction processes, adding implant layers to raise the parasitic MOSFET thresholds with respect to native thresholds, and suppressing CMOS drain-to-source and intrawell transistor-to-transistor leakage. In addition, radhard field oxide is utilized. SEE ruggedness is improved by reducing the epi thickness over that of non-radhard devices, and increasing the epi concentration near the substrate junction. A radhard PIC rated to 400 V and capable of operating at 600 V or more is provided. The inventive PIC can withstand 100 krads of TID and a heavy ion Linear Energy Transfer of 37 MeV/(mg/cm2) at full rated voltage.

Abstract: The epitaxial substrate of a semiconductor chip device has a resurf diffusion in at least one of its isolated wells in the device chip surface. The wells are separated by junction diffusions. The thickness of the epitaxial layer is reduced by placing an increased percentage of its total charge for given a breakdown voltage (punch-through voltage) in the lower portion of the layer.

Abstract: Level shift devices are formed in the high voltage termination region of an integrated circuit. The level shift devices provide a connection between the higher voltage, floating circuit and a ground referenced lower voltage circuit. The structure of the level shift devices eliminates the need for a high voltage connector to cross over the low voltage connector.

Abstract: An MOS gated semiconductor device includes a metal source contact electrode which extends across the top of a overlaying oxide layer that is formed atop the gate electrode. The source metal thus extends over the channel region to provide a physical metal shield against the migration of ionic contaminants that may be present in the plastic device housing, particularly during high temperature operation. The metal shield substantially improves the device characteristics under high temperature bias conditions.

Abstract: A monolithic IGBT and control circuit therefor are integrated into a common chip. The IGBT is formed in a first area of the chip and the control circuit is formed in a second laterally spaced area and in a P well. Means are provided to prevent hole injection from the P.sup.+ substrate into the P well during IGBT operation. The means includes a sufficient spacing between the areas; a P.sup.+ collection region between the areas or an N.sup.+ diffusion between the areas which is connected to the P.sup.+ substrate. The areas are surrounded by a common field termination structure which, however, leaves a small surface bridge between the two areas. Control conductors from the control area to the IGBT area cross over the narrow area, and not over the field terminations. A lateral PNP transistor which is integrated in the chip and is external of the IGBT area is connected to the central N.sup.

Abstract: A polysilicon field ring structure is used to eliminate any type of unwanted surface current leakage in an integrated power chip having high voltage and low voltage areas and enclosed in a plastic housing. All P-type diffusions not biased to the ground potential are surrounded by rings biased to the supply potential, and all N-type diffusions not biased to the supply potential are surrounded by rings biased to the ground potential.