Patents by Inventor Nitin Jain
Nitin Jain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11296426Abstract: A laminar phased array has a first sub-array configured to operate in one of a receive mode with a first polarity and a transmit mode with a second polarity, and a second sub-array configured to operate in one of a receive mode with the second polarity and a transmit mode with the first polarity. The first polarity is physically orthogonal to the second polarity. The array also has a controller configured to control the first and second sub-arrays so that they operate together in either 1) a receive mode or 2) a transit mode. Accordingly, both sub-arrays are configured to operate at the same time to receive signals in the first and second polarities when in the receive mode. In a corresponding manner, both sub-arrays are configured to operate at the same time to transmit signals in the first and second polarities when in the transmit mode.Type: GrantFiled: April 9, 2021Date of Patent: April 5, 2022Assignee: Anokiwave, Inc.Inventors: Timothy Carey, Nitin Jain, Jason Durbin, David W. Corman, Vipul Jain
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Publication number: 20220013922Abstract: In certain exemplary embodiments, register banks are used to allow for fast beam switching (FBS) in a phased array system. Specifically, each beam forming channel is associated with a register bank containing M register sets for configuring such things as gain/amplitude and phase parameters of the beam forming channel. The register banks for all beam forming channels can be pre-programmed and then fast beam switching circuitry allows all beam forming channels across the array to be switched to use the same register set from its corresponding register bank at substantially the same time, thereby allowing the phased array system to be quickly switched between various beam patterns and orientations. Additionally or alternatively, active power control circuitry may be used to control the amount of electrical power provided to or consumed by one or more individual beam forming channels such as to reduce DC power consumption of the array and/or to selectively change the effective directivity of the array.Type: ApplicationFiled: September 23, 2021Publication date: January 13, 2022Inventors: Kristian N. Madsen, Wade C. Allen, Jonathan P. Comeau, Robert J. McMorrow, David W. Corman, Nitin Jain, Robert Ian Gresham, Gaurav Menon, Vipul Jain
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Patent number: 11219019Abstract: The present disclosure provides a method and apparatus of handling in-device co-existence interference in a wireless communication environment. In one embodiment, a method includes detecting in-device co-existence interference between a LTE module and an ISM module in user equipment. The method further includes identifying subframes and corresponding HARQ processes in a set of subframes allocated to the LTE module which are affected by the ISM module operation. Additionally, the method includes reserving the remaining subframes and corresponding HARQ processes in the set of subframes for the LTE module operation. Furthermore, the method includes indicating to a base station that the remaining subframes and the corresponding HARQ processes are reserved for the LTE module operation to resolve the in-device co-existence interference.Type: GrantFiled: September 9, 2019Date of Patent: January 4, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Sudhir Kumar Baghel, Nitin Jain, Venkateswara Rao Manepalli
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Patent number: 11205858Abstract: This patent application describes systems, devices, and methods for element-level self-calculation of phased array vectors by a beam forming ASIC using direct calculation such as for fast beam steering.Type: GrantFiled: October 15, 2019Date of Patent: December 21, 2021Assignee: Anokiwave, Inc.Inventors: Jason Durbin, Nitin Jain
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Patent number: 11177227Abstract: A phased array has a laminar substrate, a plurality of elements on the laminar substrate forming a patch phased array, and integrated circuits on the laminar substrate. Each integrated circuit is a high frequency integrated circuit configured to control receipt and/or transmission of signals by the plurality of elements in the patch phased array. In addition, each integrated circuit has a substrate side coupled with the laminar substrate, and a back side. The phased array also has a plurality of heat sinks. Each integrated circuit is coupled with at least one of the heat sinks. At least one of the integrated circuits has a thermal interface material in conductive thermal contact with its back side. The thermal interface material thus is between the at least one integrated circuit and one of the heat sinks. Preferably, the thermal interface material has a magnetic loss tangent value of between 0.5 and 4.5.Type: GrantFiled: May 28, 2020Date of Patent: November 16, 2021Assignee: Anokiwave, Inc.Inventors: Gaurav Menon, Jonathan P. Comeau, Nitin Jain
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Publication number: 20210344099Abstract: A conditioning integrated circuit (CDIC) chip can be used to aggregate signals to/from a number of beam forming integrated circuit (BFIC) chips, and signals to/from a number of CDIC chips can be aggregated by an interface integrated circuit (IFIC) chip. The CDIC chip includes temperature compensation circuitry to adjust the gain of the transmit and receive signals as a function of temperature based on inputs from a temperature sensor. The CDIC may include a plurality of beam forming channels each having a transmit circuit and a receive circuit, a common port coupled to the beam forming channels for selectively providing a common transmit signal to the beam forming channels and receiving a common receive signal from the beam forming channels, and a temperature compensation circuit configured to provide variable attenuation to the common transmit signal and the common receive signal based on a temperature sense signal.Type: ApplicationFiled: July 7, 2021Publication date: November 4, 2021Inventors: Kristian N. Madsen, Robert J. McMorrow, David W. Corman, Nitin Jain, Robert Ian Gresham, Gaurav Menon, Vipul Jain, Jonathan P. Comeau, Shmuel Ravid
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Publication number: 20210328345Abstract: A phased array system has a plurality of beam-forming elements, and a plurality of beam-forming integrated circuits in communication with the beam-forming elements. Each beam-forming integrated circuit has a corresponding register bank with a plurality of addressable and programmable register sets. In addition, each beam-forming integrated circuit has at least two different types of beam-forming ports. Specifically, each beam-forming element has a serial data port for receiving serial messages, and a parallel mode data port for receiving broadcast messages. Both the serial and broadcast messages manage the data in its register bank. The beam-forming integrated circuits receive the broadcast messages in parallel with the other beam-forming integrated circuits, while the beam-forming integrated circuits receive the serial messages serially—sequentially with regard to other beam-forming integrated circuits.Type: ApplicationFiled: June 30, 2021Publication date: October 21, 2021Inventors: Vipul Jain, Scott Humphreys, David W. Corman, Robert Ian Gresham, Kristian N. Madsen, Robert J. McMorrow, Jonathan P. Comeau, Nitin Jain, Gaurav Menon
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Publication number: 20210320427Abstract: A phased array includes a laminar substrate having both 1) a plurality of elements forming a patch phased array, and 2) a plurality of integrated circuits. Each integrated circuit is configured to control receipt and transmission of signals by the plurality of elements in the patch phased array. The integrated circuits also are configured to operate the phased array at one or more satellite frequencies—to transmit signals to and/or receive signals from a satellite. Each integrated circuit physically couples with one corresponding element so that incoming signals are received by the corresponding element in a first polarization, and outgoing signals are transmitted by the corresponding element in a second polarization. The phased array isolates the transmit signals from the receive signals by orienting the first and second polarizations differently.Type: ApplicationFiled: April 16, 2021Publication date: October 14, 2021Inventors: David W. Corman, Vipul Jain, Timothy Carey, Nitin Jain
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Patent number: 11133603Abstract: In certain exemplary embodiments, register banks are used to allow for fast beam switching (FBS) in a phased array system. Specifically, each beam forming channel is associated with a register bank containing M register sets for configuring such things as gain/amplitude and phase parameters of the beam forming channel. The register banks for all beam forming channels can be pre-programmed and then fast beam switching circuitry allows all beam forming channels across the array to be switched to use the same register set from its corresponding register bank at substantially the same time, thereby allowing the phased array system to be quickly switched between various beam patterns and orientations. Additionally or alternatively, active power control circuitry may be used to control the amount of electrical power provided to or consumed by one or more individual beam forming channels such as to reduce DC power consumption of the array and/or to selectively change the effective directivity of the array.Type: GrantFiled: November 16, 2020Date of Patent: September 28, 2021Assignee: Anokiwave, Inc.Inventors: Kristian N. Madsen, Wade C. Allen, Jonathan P. Comeau, Robert J. McMorrow, David W. Corman, Nitin Jain, Robert Ian Gresham, Gaurav Menon, Vipul Jain
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Publication number: 20210296784Abstract: A laminar phased array has a first sub-array configured to operate in one of a receive mode with a first polarity and a transmit mode with a second polarity, and a second sub-array configured to operate in one of a receive mode with the second polarity and a transmit mode with the first polarity. The first polarity is physically orthogonal to the second polarity. The array also has a controller configured to control the first and second sub-arrays so that they operate together in either 1) a receive mode or 2) a transit mode. Accordingly, both sub-arrays are configured to operate at the same time to receive signals in the first and second polarities when in the receive mode. In a corresponding manner, both sub-arrays are configured to operate at the same time to transmit signals in the first and second polarities when in the transmit mode.Type: ApplicationFiled: April 9, 2021Publication date: September 23, 2021Inventors: Timothy Carey, Nitin Jain, Jason Durbin, David W. Corman, Vipul Jain
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Patent number: 11081792Abstract: A phased array system has a plurality of beam-forming elements, and a plurality of beam-forming integrated circuits in communication with the beam-forming elements. Each beam-forming integrated circuit has a corresponding register bank with a plurality of addressable and programmable register sets. In addition, each beam-forming integrated circuit has at least two different types of beam-forming ports. Specifically, each beam-forming element has a serial data port for receiving serial messages, and a parallel mode data port for receiving broadcast messages. Both the serial and broadcast messages manage the data in its register bank. The beam-forming integrated circuits receive the broadcast messages in parallel with the other beam-forming integrated circuits, while the beam-forming integrated circuits receive the serial messages serially—sequentially with regard to other beam-forming integrated circuits.Type: GrantFiled: March 7, 2019Date of Patent: August 3, 2021Assignee: Anokiwave, Inc.Inventors: Vipul Jain, Scott Humphreys, David W. Corman, Robert Ian Gresham, Kristian N. Madsen, Robert J. McMorrow, Jonathan P. Comeau, Nitin Jain, Gaurav Menon
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Patent number: 11082006Abstract: A clock signal is generated with an oscillator. A crystal oscillator core within the oscillator circuit is switched on to produce first and second oscillation signals that are approximately opposite in phase. When a difference between a voltage of the first oscillation signal and a voltage of the second oscillation signal exceeds an upper threshold range, the crystal oscillator core is switched off. When the difference between the voltage of the first oscillation signal and the voltage of the second oscillation signal falls below the upper threshold range, the crystal oscillator core is switched back on. This operation is repeated so as to produce the clock signal.Type: GrantFiled: December 4, 2019Date of Patent: August 3, 2021Assignee: STMicroelectronics International N.V.Inventors: Anand Kumar, Nitin Jain
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Publication number: 20210235282Abstract: A beamforming integrated circuit system is configured to optimize performance. Among other things, the system may run at a lower power than conventional integrated circuits, selectively disable branches to control certain system functions, and/or selectively position ground pads around receiving pads to enhance isolation. The system also may use a beamforming integrated circuit as a distribution circuit for a number of similar or like beamforming integrated circuits.Type: ApplicationFiled: December 24, 2018Publication date: July 29, 2021Applicant: ANOKIWAVE, INC.Inventors: Pavel Brechko, David W. Corman, Vipul Jain, Shamsun Nahar, Jason Durbin, Nitin Jain
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Patent number: 11063336Abstract: A conditioning integrated circuit (CDIC) chip can be used to aggregate signals to/from a number of beam forming integrated circuit (BFIC) chips, and signals to/from a number of CDIC chips can be aggregated by an interface integrated circuit (IFIC) chip. The CDIC chip includes temperature compensation circuitry to adjust the gain of the transmit and receive signals as a function of temperature based on inputs from a temperature sensor. The CDIC may include a plurality of beam forming channels each having a transmit circuit and a receive circuit, a common port coupled to the beam forming channels for selectively providing a common transmit signal to the beam forming channels and receiving a common receive signal from the beam forming channels, and a temperature compensation circuit configured to provide variable attenuation to the common transmit signal and the common receive signal based on a temperature sense signal.Type: GrantFiled: April 4, 2019Date of Patent: July 13, 2021Assignee: Anokiwave, Inc.Inventors: Kristian N. Madsen, Robert J. McMorrow, David W. Corman, Nitin Jain, Robert Ian Gresham, Gaurav Menon, Vipul Jain, Jonathan P. Comeau, Shmuel Ravid
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Patent number: 11051773Abstract: A system is provided that includes at least one detector and a processing unit. The at least one detector is configured to acquire imaging information. The processing unit is operably coupled to the at least one detector, and is configured to acquire the imaging information from the at least one detector. The processing unit is configured to acquire patient scanning information for an imaging operation, determine a target activity based on the patient scanning information, determine a target time for performing the imaging operation corresponding to the target activity, perform the imaging operation at the target time to acquire targeted imaging information; and reconstruct an image using the targeted imaging information.Type: GrantFiled: December 4, 2017Date of Patent: July 6, 2021Assignee: GENERAL ELECTRIC COMPANYInventors: Nitin Jain, Charles Stearns, Savitha V S
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Patent number: 11048492Abstract: Embodiments of the invention provide systems and methods for applying a patch or a change to a set of binary modules executing on and used by resources of a computing cluster while reducing the downtime of those resources. According to one embodiment, applying a patch to a plurality of binary modules on a computing cluster can comprise identifying resources on one or more of a plurality of nodes of the cluster. Additionally, each of the plurality of binary modules on one or more of the nodes of the cluster can be identified. A graph can be generated logically representing the cluster. Groups within the binary modules and resources can be identified based on the graph. Patches can be applied to the binary modules based on the identified groups. Patching binary modules based on the identified groups can comprise patching all of the binary modules of an identified group together.Type: GrantFiled: August 24, 2010Date of Patent: June 29, 2021Assignee: ORACLE INTERNATIONAL CORPORATIONInventors: Nitin Jain, Tim Misner
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Patent number: 11011853Abstract: A phased array includes a laminar substrate having both 1) a plurality of elements forming a patch phased array, and 2) a plurality of integrated circuits. Each integrated circuit is configured to control receipt and transmission of signals by the plurality of elements in the patch phased array. The integrated circuits also are configured to operate the phased array at one or more satellite frequencies—to transmit signals to and/or receive signals from a satellite. Each integrated circuit physically couples with one corresponding element so that incoming signals are received by the corresponding element in a first polarization, and outgoing signals are transmitted by the corresponding element in a second polarization. The phased array isolates the transmit signals from the receive signals by orienting the first and second polarizations differently.Type: GrantFiled: September 16, 2016Date of Patent: May 18, 2021Assignee: Anokiwave, Inc.Inventors: David W. Corman, Vipul Jain, Timothy Carey, Nitin Jain
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Patent number: 10998640Abstract: A laminar phased array has a first sub-array configured to operate in one of a receive mode with a first polarity and a transmit mode with a second polarity, and a second sub-array configured to operate in one of a receive mode with the second polarity and a transmit mode with the first polarity. The first polarity is physically orthogonal to the second polarity. The array also has a controller configured to control the first and second sub-arrays so that they operate together in either 1) a receive mode or 2) a transit mode. Accordingly, both sub-arrays are configured to operate at the same time to receive signals in the first and second polarities when in the receive mode. In a corresponding manner, both sub-arrays are configured to operate at the same time to transmit signals in the first and second polarities when in the transmit mode.Type: GrantFiled: May 15, 2019Date of Patent: May 4, 2021Assignee: Anokiwave, Inc.Inventors: Timothy Carey, Nitin Jain, Jason Durbin, David W. Corman, Vipul Jain
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Patent number: 10985819Abstract: This patent application describes systems, devices, and methods for element-level self-calculation of phased array vectors by a beam forming ASIC using interpolation and a look-up table for calculation of phase setting values such as for fast beam steering.Type: GrantFiled: October 15, 2019Date of Patent: April 20, 2021Assignee: Anokiwave, Inc.Inventors: Jason Durbin, Nitin Jain
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Publication number: 20210075125Abstract: In certain exemplary embodiments, register banks are used to allow for fast beam switching (FBS) in a phased array system. Specifically, each beam forming channel is associated with a register bank containing M register sets for configuring such things as gain/amplitude and phase parameters of the beam forming channel. The register banks for all beam forming channels can be pre-programmed and then fast beam switching circuitry allows all beam forming channels across the array to be switched to use the same register set from its corresponding register bank at substantially the same time, thereby allowing the phased array system to be quickly switched between various beam patterns and orientations. Additionally or alternatively, active power control circuitry may be used to control the amount of electrical power provided to or consumed by one or more individual beam forming channels such as to reduce DC power consumption of the array and/or to selectively change the effective directivity of the array.Type: ApplicationFiled: November 16, 2020Publication date: March 11, 2021Inventors: Kristian N. Madsen, Wade C. Allen, Jonathan P. Comeau, Robert J. McMorrow, David W. Corman, Nitin Jain, Robert Ian Gresham, Gaurav Menon, Vipul Jain