Abstract: The present invention relates to a semiconductor device comprising at least one n-channel field effect transistor (n-FET). Specifically, the n-FET comprises first and second patterned stressor layers that both contain a carbon-substituted and tensilely stressed single crystal semiconductor. The first patterned stressor layer has a first carbon concentration and is located in source and drain (S/D) extension regions of the n-FET at a first depth. The second patterned stressor layer has a second, higher carbon concentration and is located in S/D regions of the n-FET at a second, deeper depth. Such an n-FET with the first and second patterned stressor layers of different carbon concentration and different depths provide improved stress profile for enhancing electron mobility in the channel region of the n-FET.

Abstract: A structure, semiconductor device and method having a substantially L-shaped silicide element for a contact are disclosed. The substantially L-shaped silicide element, inter alia, reduces contact resistance and may allow increased density of CMOS circuits. In one embodiment, the structure includes a substantially L-shaped silicide element including a base member and an extended member, wherein the base member extends at least partially into a shallow trench isolation (STI) region such that a substantially horizontal surface of the base member directly contacts a substantially horizontal surface of the STI region; and a contact contacting the substantially L-shaped silicide element. The contact may include a notch region for mating with the base member and a portion of the extended member, which increases the silicide-to-contact area and reduces contact resistance.

Abstract: The present invention relates to a semiconductor device including at least one n-channel field effect transistor (n-FET). Specifically, the n-FET includes first and second patterned stressor layers that both contain a carbon-substituted and tensilely stressed single crystal semiconductor. The first patterned stressor layer has a first carbon concentration and is located in source and drain (S/D) extension regions of the n-FET at a first depth. The second patterned stressor layer has a second, higher carbon concentration and is located in S/D regions of the n-FET at a second, deeper depth. Such an n-FET with the first and second patterned stressor layers of different carbon concentration and different depths provide improved stress profile for enhancing electron mobility in the channel region of the n-FET.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. A preferred embodiment includes providing a workpiece, forming a gate dielectric material over the workpiece, the gate dielectric material comprising an insulator and at least one metal element, and forming a conductive material over the gate dielectric material. The conductive material comprises the at least one metal element of the gate dielectric material.

Abstract: A method for providing a dual stress memory technique in a semiconductor device including an nFET and a PFET and a related structure are disclosed. One embodiment of the method includes forming a tensile stress layer over the nFET and a compressive stress layer over the pFET, annealing to memorize stress in the semiconductor device and removing the stress layers. The compressive stress layer may include a high stress silicon nitride deposited using a high density plasma (HDP) deposition method. The annealing step may include using a temperature of approximately 400-1200° C. The high stress compressive silicon nitride and/or the anneal temperatures ensure that the compressive stress memorization is retained in the pFET.

Abstract: Structures and methods for forming keyhole shaped regions for isolation and/or stressing the substrate are shown. In a first embodiment, we form an inverted keyhole shaped trench in the substrate in the first opening preferably using a two step etch. Next, we fill the inverted keyhole trench with a material that insulates and/or creates stress on the sidewalls of the inverted keyhole trench. In a second embodiment, we form a keyhole stressor region adjacent to the gate and isolation structures. The keyhole stressor region creates stress near the channel region of the FET to improve FET performance. The stressor region can be filled with an insulator or a semiconductor material.

Abstract: A method of forming a salicide on a semiconductor device includes depositing a first refractory metal layer over a silicon region of a substrate, depositing a near-noble metal layer over the first refractory metal layer, and depositing a second refractory metal layer over the near-noble metal layer. The semiconductor device is annealed in a first annealing process to form a silicide layer abutting the doped region of the semiconductor device. Un-reacted portions of the near-noble metal layer and the second refractory metal layer are removed. The device may be annealed in an optional second annealing process to convert the silicide layer to a low resistance phase silicide material. Junction leakage and bridging are minimized or eliminated by embodiments of the present invention, and a smoother silicided surface is achieved.

Abstract: A method of forming a salicide on a semiconductor device includes depositing a first refractory metal layer over a silicon region of a substrate, depositing a near-noble metal layer over the first refractory metal layer, and depositing a second refractory metal layer over the near-noble metal layer. The semiconductor device is annealed in a first annealing process to form a silicide layer abutting the doped region of the semiconductor device. Un-reacted portions of the near-noble metal layer and the second refractory metal layer are removed. The device may be annealed in an optional second annealing process to convert the silicide layer to a low resistance phase silicide material. Junction leakage and bridging are minimized or eliminated by embodiments of the present invention, and a smoother silicided surface is achieved.

Abstract: A method for forming a planarized field effect transistor (FET) is disclosed. In an exemplary embodiment of the invention, the method includes defining an active semiconductor region upon a substrate, the active semiconductor region further comprising a pair of mesa regions therein. A source region is defined within a top surface of one of the pair of mesa regions, and a drain region is defined within a top surface of the other of the pair of mesa regions. Then, a gate material is deposited between the pair of mesa regions, and the gate material is planarized to form a gate. Thereby, a top surface of the gate is substantially planar with the source and drain regions.

Abstract: A method for forming a planarized field effect transistor (FET) is disclosed. In an exemplary embodiment of the invention, the method includes defining an active semiconductor region upon a substrate, the active semiconductor region further comprising a pair of mesa regions therein. A source region is defined within a top surface of one of the pair of mesa regions, and a drain region is defined within a top surface of the other of the pair of mesa regions. Then, a gate material is deposited between the pair of mesa regions, and the gate material is planarized to form a gate. Thereby, a top surface of the gate is substantially planar with the source and drain regions.

Abstract: A method for forming a planarized field effect transistor (FET) is disclosed. In an exemplary embodiment of the invention, the method includes defining an active semiconductor region upon a substrate, the active semiconductor region further comprising a pair of mesa regions therein. A source region is defined within a top surface of one of the pair of mesa regions, and a drain region is defined within a top surface of the other of the pair of mesa regions. Then, a gate material is deposited between the pair of mesa regions, and the gate material is planarized to form a gate. Thereby, a top surface of the gate is substantially planar with the source and drain regions.

Abstract: A method for forming a JOI structure which allows for reduction in both source/drain junction leakage and capacitance is provided. In the inventive method, an insulator layer is formed under the source/drain regions, but not under the channel region. The insulator layer is formed in the present invention after forming the gate stack region and recessing the semiconductor surface surrounding the gate stack region, followed by deposition of a conductive material such as polysilicon and, optionally, heavy source/drain diffusion formation.

Abstract: A field effect transistor (FET) is disclosed. In an exemplary embodiment of the invention, the FET includes an active semiconductor region defined upon a substrate, the active semiconductor region further having a mesa region formed therein. The FET also includes a gate formed within the active semiconductor region, the gate abutting the mesa region along one side thereof. The FET further includes a source region defined within a first area of the semiconductor region, the first region being located over an insulating layer, and a drain region defined within a second area of the semiconductor region, the second area also being located over the insulating layer. The first and second areas of the semiconductor region are located on opposite sides of the mesa region, and the insulating layer isolates the source region and the drain region from the substrate. In another exemplary embodiment, one of the source region or drain region is defined within a top surface of the mesa region.

Abstract: A method for forming a JOI structure which allows for reduction in both source/drain junction leakage and capacitance is provided. In the inventive method, an insulator layer is formed under the source/drain regions, but not under the channel region. The insulator layer is formed in the present invention after forming the gate stack region and recessing the semiconductor surface surrounding the gate stack region, followed by deposition of a conductive material such as polysilicon and, optionally, heavy source/drain diffusion formation.

Abstract: A method for forming a field effect transistor (FET) is disclosed. In an exemplary embodiment of the invention, the method includes defining an active semiconductor region upon a substrate, the active semiconductor region further having a mesa region formed therein. A gate is formed within the active semiconductor region, the gate abutting the mesa region along one side thereof. Then, a source region is defined within a first area of the semiconductor region, the first region being located over an insulating layer. A drain region is defined within a second area of the semiconductor region, the second area also being located over the insulating layer. The first and second areas of the semiconductor region are located on opposite sides of the mesa region, and the insulating layer isolates the source region and the drain region from the substrate.

Abstract: A method for forming a planarized field effect transistor (FET) is disclosed. In an exemplary embodiment of the invention, the method includes defining an active semiconductor region upon a substrate, the active semiconductor region further comprising a pair of mesa regions therein. A source region is defined within a top surface of one of the pair of mesa regions, and a drain region is defined within a top surface of the other of the pair of mesa regions. Then, a gate material is deposited between the pair of mesa regions, and the gate material is planarized to form a gate. Thereby, a top surface of the gate is substantially planar with the source and drain regions.

Abstract: A patterned buried insulator is formed beneath the source and drain by forming a mask over the body area and implanting a dose of n or p type ions in the areas where the source and drains will be formed, then etching the STI and etching out the implanted area. A light oxidation is followed by a conformal oxide deposition in the STI and also in the etched area, thereby forming the buried oxide only where desired.

Abstract: A patterned buried insulator is formed beneath the source and drain by forming a mask over the body area and implanting a dose of n or p type ions in the areas where the source and drains will be formed, then etching the STI and etching out the implanted area. A light oxidation is followed by a conformal oxide deposition in the STI and also in the etched area, thereby forming the buried oxide only where desired.

Abstract: Transistors having self-aligned dielectric layers under the source/drain contacts are formed by constructing transistors up to the LDD implant; etching STI oxide selective to Si and nitride to form a self-aligned contact recess; depositing an insulating layer in the bottom of the contact recess; recessing the insulating layer to leave room for a conductive contact layer; depositing the contact layer to make contact on a vertical surface to the Si underneath the gate sidewalls; recessing the contact layer; forming interlayer dielectric and interconnect to complete the circuit.

Abstract: A logic circuit including an embedded DRAM achieves process integration by simultaneously forming the strap connecting the memory cell capacitor with the pass transistor and a buried dielectric layer isolating the logic transistor sources and drains from the substrate.