Abstract: In a bulk silicon process, an insulating layer is placed under the portion of the source and drain used for contacts, thereby reducing junction capacitance. The processing involves a smaller than usual transistor area that is not large enough to hold the contacts, which are placed in an aperture cut into the shallow trench isolation.

Abstract: An apparatus and method for detecting a defective array of NVRAM cells. A counter is provided which times an erase time interval for the NVRAM cells during a regular erase function. The computed erase interval is compared with a maximum erase interval to determine at least a first characteristic which indicates the block of NVRAMs is at the end of its useful life. A second characteristic is determined by computing the slope in the erase time function versus the number of simulated erase functions. When the slope of the erase function exceeds a maximum slope, the NVRAM array is determined to be at the end of its useful life.

Abstract: An integrated circuit using high-performance bipolar and CMOS transistor elements on a single chip is fabricated by a simplified process requiring minimal, if any, changes in the process used for forming either type of device in accordance with a variety of possible device designs. The method according to the invention makes maximal use of self-aligned and self-masking processes to reduce the number of processing steps. The number of processing steps is further reduced by performing some steps concurrently on different device types. Further, the masking steps which are employed are reasonably misregistration tolerant, resulting in high manufacturing yield for the process. Consequently, the process according to the invention substantially eliminates the existence of trade-offs between element performance, integration density and process complexity and cost when plural technologies are integrated on the same chip.

Abstract: Improved packing density as well as improved performance and manufacturing yield is achieved in an electrically programmable memory by confining floating gate structures between isolation structures covered with a thin nitride layer. The confinement of the floating gate is achieved by planarization, preferably with a self-limiting chemical/mechanical polishing process, to the surface of the nitride layer covering the isolation structures. Gate oxide and control electrode connections can then be formed on a substantially planar surface without compromising the quality of the gate oxide or breakdown voltage the device must withstand for programming. Since severe topology is avoided over which these connections are formed, improved formation of low resistance connections, possibly including metal connections, are possible and allow scaling of transistors of the memory cells to be scaled to sizes not previously possible.

Abstract: A process for fabricating a high density memory array. N-type impurities are implanted in a p-type substrate to form continuous rails of diffusion that have a substantially flat contour. Each rail of diffusion defines a corresponding bit line. Each rail defines the source and drain region of each pair of adjacent memory array cells associated with the bit line. In one embodiment, multiple layers of polysilicon are utilized to form a control gate, a floating gate, a source and a drain. In another embodiment, multiple layers of polysilicon are utilized to form an auxiliary gate, a floating gate, a source and a drain. In both embodiments, the polysilicon layers self-aligned to substantially reduce polysilicon layer-overlap so as to minimize parasitic capacitances. Domino and Skippy Domino schemes are used to program and read the memory array cells.

Abstract: A process for fabricating a high density memory array. N-type impurities are implanted in a p-type substrate to form continuous rails of diffusion that have a substantially flat contour. Each rail of diffusion defines a corresponding bit line. Each rail defines the source and drain region of each pair of adjacent memory array cells associated with the bit line. In one embodiment, multiple layers of polysilicon are utilized to form a control gate, a floating gate, a source and a drain. In another embodiment, multiple layers of polysilicon are utilized to form an auxiliary gate, a floating gate, a source and a drain. In both embodiments, the polysilicon layers self-aligned to substantially reduce polysilicon layer-overlap so as to minimize parasitic capacitances. Domino and Skippy Domino schemes are used to program and read the memory array cells.

Abstract: A process for fabricating a high density memory array. N-type impurities are implanted in a p-type substrate to form continuous rails of diffusion that have a substantially flat contour. Each rail of diffusion defines a corresponding bit line. Each rail defines the source and drain region of each pair of adjacent memory array cells associated with the bit line. In one embodiment, multiple layers of polysilicon are utilized to form a control gate, a floating gate, a source and a drain. In another embodiment, multiple layers of polysilicon are utilized to form an auxiliary gate, a floating gate, a source and a drain. In both embodiments, the polysilicon layers self-aligned to substantially reduce polysilicon layer-overlap so as to minimize parasitic capacitances. Domino and Skippy Domino schemes are used to program and read the memory array cells.

Abstract: An EEPROM cell capable of being formed at high integration density achieves improved coupling ratio, reduced programming voltage and improved operating margins by provision of a dielectric on lateral sides of the floating gate and a composite control gate electrode structure having conductive sidewalls ohmically connected to a control electrode and overlapping the sides of the floating gate. A methodology for manufacture of this EEPROM cell features a plurality of self-aligned processes producing features of sub-lithographic dimensions.

Abstract: Improved packing density as well as improved performance and manufacturing yield is achieved in an electrically programmable memory by confining floating gate structures between isolation structures covered with a thin nitride layer. The confinement of the floating gate is achieved by planarization, preferably with a self-limiting chemical/mechanical polishing process, to the surface of the nitride layer covering the isolation structures. Gate oxide and control electrode connections can then be formed on a substantially planar surface without compromising the quality of the gate oxide or breakdown voltage the device must withstand for programming. Since severe topology is avoided over which these connections are formed, improved formation of low resistance connections, possibly including metal connections, are possible and allow scaling of transistors of the memory cells to be scaled to sizes not previously possible.

Abstract: Improved packing density as well as improved performance and manufacturing yield is achieved in an electrically programmable memory by confining floating gate structures between isolation structures covered with a thin nitride layer. The confinement of the floating gate is achieved by planarization, preferably with a self-limiting chemical/mechanical polishing process, to the surface of the nitride layer covering the isolation structures. Gate oxide and control electrode connections can then be formed on a substantially planar surface without compromising the quality of the gate oxide or breakdown voltage the device must withstand for programming. Since severe topology is avoided over which these connections are formed, improved formation of low resistance connections, possibly including metal connections, are possible and allow scaling of transistors of the memory cells to be scaled to sizes not previously possible.

Abstract: A process for fabricating a high density memory array. N-type impurities are implanted in a p-type substrate to form continuous rails of diffusion that have a substantially flat contour. Each rail of diffusion defines a corresponding bit line. Each rail defines the source and drain region of each pair of adjacent memory array cells associated with the bit line. In one embodiment, multiple layers of polysilicon are utilized to form a control gate, a floating gate, a source and a drain. In another embodiment, multiple layers of polysilicon are utilized to form an auxiliary gate, a floating gate, a source and a drain. In both embodiments, the polysilicon layers self-aligned to substantially reduce polysilicon layer-overlap so as to minimize parasitic capacitances. Domino and Skippy Domino schemes are used to program and read the memory array cells.

Abstract: A method of forming a MOS DRAM cell having a trench capacitor in which the strap connection to the trench capacitor, the source, drain, and isolation are all raised above the surface of the single crystal silicon includes the steps of forming the trench capacitors, depositing a blanket gate stack including the gate oxide and a set of gate layers, and then depositing isolation members in apertures etched in the gate stack using the gate oxide as an etch stop. The same sidewalls that are used to form an LDD source and drain form a self-aligned aperture for a surface strap that insulates the strap from misaligned portions of the gate stack.

Abstract: An SOI wafer has a device layer of initial thickness that is formed into a set of mesas in the interval between which a temporary layer of polysilicon is deposited to a precisely controlled thickness. This polysilicon is entirely converted in a self-limiting process to an oxide etch stop having a thickness much smaller than the initial thickness. The mesas are thinned by a chemical mechanical polishing technique until the mesa is the same level as the top surface of the new oxide. The etch stop layer of oxide is not removed but serves both as an isolating layer to provide dielectric isolation between mesas in the final circuit and also as a visual gauge to determine the time when the polishing process should stop.

Abstract: A method of forming a SOI integrated circuit includes defining thin silicon mesas by etching a device layer down to the underlying insulator, forming a nitride bottom polish stop in the bottom of the apertures by a low temperature PECVD process, with nitride sidewalls on the silicon mesas being susceptible to easy removal, so that no hard material is present during a chemical-mechanical polishing step to thin the device layer down to less than 1000.ANG., and filling the apertures with a temporary layer of polysilicon to provide mechanical support to the edges of the device layer during the polishing operation.

Abstract: A compressed vertical bipolar transistor configuration that eliminates one side of the standard symmetrical base contact, while also eliminating the requirement for a collector contact reach-thru. The bipolar transistor comprises: a collector layer; a base layer disposed over the collector layer; an emitter layer disposed over the base layer; a first sidewall insulating layer disposed adjacent to and in contact with one side of the emitter layer, the base layer, and at least a portion of the collector layer; a second sidewall insulating layer disposed adjacent to and in contact with another side of the emitter layer and at least a portion of the base layer; and a base contact extension layer formed from heavily doped semiconductor material of the same conductivity type as the base layer, said base contact extension layer being in contact with an extending laterally from another side of the base layer.

Abstract: A compressed vertical bipolar transistor configuration that eliminates one side of the standard symmetrical base contact, while also eliminating the requirement for a collector contact reach-thru. The bipolar transistor comprises: a collector layer; a base layer disposed over the collector layer; an emitter layer disposed over the base layer; a first sidewall insulating layer disposeed adjacent to and in contact with one side of the emitter layer, the base layer, and at least a portion of the collector layer; a second sidewall insulating layer disposed adjacent to and in contact with another side of the emitter layer and at least a portion of the base layer; and a base contact extension layer formed from heavily doped semiconductor material of the same conductivity type as the base layer, said base contact extension layer being in contact with and extending laterally from another side of the base layer.

Abstract: A method for fabricating a Bi-CMOS device is disclosed herein, which device can include both vertical PNP and NPN components. The process steps include forming the reach-through N+ subcollector to the bipolar device without extra processing steps; combining into one mask the threshold adjust/well implants with self-aligned isolation leakage protection implants by using a self-aligned, removable oxide mask prior to field isolation; using a resist etch-back scheme to protect against emitter-to-base punch-through while self-aligning the pedestal and base; and also providing for the removal of the gate oxide at the emitter while maintaining it at the FET, without extra masks.The device incorporates similar structural featues between the bi-polar and FET devices. The NPN and pFET can share the same well and a P+ diffusion (the p+ extrinsic base is the same as the p+ source). Also, the pnp and nFET can share the same well and an n+ diffusion.

Abstract: A method for forming fully recessed (planar) isolation regions on a semiconductor for the manufacture of CMOS integrated circuits, and the resulting semiconductor structure, comprising in a P doped silicon substrate with mesas formed therein, forming low viscosity sidewall spacers of borosilicate glass in contact with the sidewalls of those mesas designated to have N-channel devices formed therein; then filling the trenches in the substrate adjacent to the mesas with TEOS; and heating the structure until the boron in the sidewall spacers diffuses into the sidewalls of the designated mesas to form channel stops. These sidewall spacers reduce the occurrence of cracks in the TEOS by relieving internal mechanical stress therein and permit the formation of channel stops via diffusion, thereby permitting mesa walls to be substantially vertical.

Abstract: A chemical-mechanical (chem-mech) method for removing SiO.sub.2 protuberances at the surface of a silicon chip, such protuberances including "bird's heads". A thin etch stop layer of Si.sub.3 N.sub.4 is deposited onto the wafer surface, which is then chem-mech polished with a SiO.sub.2 water based slurry. The Si.sub.3 N.sub.4 acts as a polishing or etch stop barrier layer only on the planar portions of the wafer surface. The portions of the Si.sub.3 N.sub.4 layer located on the top and at the sidewalls of the "bird's heads" and the underlying SiO.sub.2 protuberances are removed to provide a substantially planar integrated structure.

Abstract: A field effect transistor of asymmetrical structure comprises: a semiconductor substrate of first conductivity type; source and drain regions of second conductivity type disposed in a surface of the substrate and spaced apart by a channel region; and a single, lightly doped extension of the drain region into the channel, the extension being of the second conductivity type and of a lower dopant concentration than the drain region. The transistor can further beneficially comprise a halo region of the first conductivity type in the substrate generally surrounding only the source region.