Patents by Inventor Noboru Akiyama

Noboru Akiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8064235
    Abstract: In order to reduce parasitic inductance of a main circuit in a power supply circuit, a non-insulated DC-DC converter is provided including a circuit in which a power MOS•FET for a high-side switch and a power MOS•FET for a low-side switch are connected in series. In the non-insulated DC-DC converter, the power MOS•FET for the high-side switch is formed by a p-channel vertical MOS•FET, and the power MOS•FET for the low-side switch is formed by an n channel vertical MOS•FET. Thus, a semiconductor chip formed with the power MOS•FET for the high-side switch and a semiconductor chip formed with the power MOS•FET for the low-side switch are mounted over the same die pad and electrically connected to each other through the die pad.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: November 22, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Masaki Shiraishi, Noboru Akiyama, Tomoaki Uno, Nobuyoshi Matsuura
  • Publication number: 20110278655
    Abstract: Parasitic inductance of the main circuit of a power source unit is reduced. In a non-insulated DC-DC converter having a circuit in which a power MOSFET for high side switch and a power MOSFET for low side switch are connected in series, the power MOSFET for high side switch and the power MOSFET for low side switch are formed of n-channel vertical MOSFETs, and a source electrode of the power MOSFET for high side switch and a drain electrode of the power MOSFET for low side switch are electrically connected via the same die pad.
    Type: Application
    Filed: July 28, 2011
    Publication date: November 17, 2011
    Applicant: Renesas Electronics Corporation
    Inventors: Takayuki Hashimoto, Noboru Akiyama, Masaki Shiraishi, Tetsuya Kawashima
  • Patent number: 8049479
    Abstract: In a non-isolated DC/DC converter, a reference potential for a low-side pre-driver which drives a gate of a low-side MOSFET is applied from a portion except for a main circuit passing through a high-side MOSFET and the low-side MOSFET so that a parasitic inductance between a source of the low-side MOSFET and the pre-driver is increased without increasing the sum of parasitic inductances in the main circuit and negative potential driving of the gate of the low-side MOSFET can be performed and a self turn-on phenomenon can be prevented without adding any member and changing drive system.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: November 1, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Masaki Shiraishi, Takayuki Hashimoto, Noboru Akiyama
  • Patent number: 8044520
    Abstract: A power supply capable of reducing loss of large current and high frequency. In an MCM for power supply in which a high-side power MOSFET chip, a low-side power MOSFET chip and a driver IC chip driving them are sealed in one sealing material (a capsulating insulation resin), a wiring length of a wiring DL connecting an output terminal of the driver IC chip to a gate terminal of the low-side power MOSFET chip or a source terminal is made shorter than a wiring length of a wiring DH connecting the output terminal of the driver IC chip to a gate terminal of the high-side power MOSFET chip or a source terminal. Further, the number of the wiring DL is made larger than the number of the wiring DH.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: October 25, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Noboru Akiyama, Takayuki Hashimoto, Masaki Shiraishi, Tetsuya Kawashima, Koji Tateno, Nobuyoshi Matsuura
  • Patent number: 8008699
    Abstract: Parasitic inductance of the main circuit of a power source unit is reduced. In a non-insulated DC-DC converter having a circuit in which a power MOSFET for high side switch and a power MOSFET for low side switch are connected in series, the power MOSFET for high side switch and the power MOSFET for low side switch are formed of n-channel vertical MOSFETs, and a source electrode of the power MOSFET for high side switch and a drain electrode of the power MOSFET for low side switch are electrically connected via the same die pad.
    Type: Grant
    Filed: March 10, 2010
    Date of Patent: August 30, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Takayuki Hashimoto, Noboru Akiyama, Masaki Shiraishi, Tetsuya Kawashima
  • Patent number: 7928505
    Abstract: The vertical trench MOSFET comprises: an N type epitaxial region formed on an upper surface of an N+ type substrate having a drain electrode on a lower surface thereof; a gate trench extending from a front surface into the N type epitaxial region; a gate electrode positioned in the gate trench so as to interpose an insulator; a channel region formed on the N type epitaxial region; a source region formed on the channel region; a source electrode formed on the source region; a source trench extending from the front surface into the N type epitaxial region; and a trench-buried source electrode positioned in the source trench so as to interpose an insulator, wherein the source electrode contacts with the trench-buried source electrode.
    Type: Grant
    Filed: December 2, 2008
    Date of Patent: April 19, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Takashi Hirao, Takayuki Hashimoto, Noboru Akiyama
  • Publication number: 20110037450
    Abstract: In order to reduce parasitic inductance of a main circuit in a power supply circuit, a non-insulated DC-DC converter is provided including a circuit in which a power MOS•FET for a high-side switch and a power MOS•FET for a low-side switch are connected in series. In the non-insulated DC-DC converter, the power MOS•FET for the high-side switch is formed by a p-channel vertical MOS•FET, and the power MOS•FET for the low-side switch is formed by an n channel vertical MOS•FET. Thus, a semiconductor chip formed with the power MOSFET for the high-side switch and a semiconductor chip formed with the power MOS•FET for the low-side switch are mounted over the same die pad and electrically connected to each other through the die pad.
    Type: Application
    Filed: October 27, 2010
    Publication date: February 17, 2011
    Inventors: Masaki Shiraishi, Noboru Akiyama, Tomoaki Uno, Nobuyoshi Matsuura
  • Publication number: 20100327348
    Abstract: In a lateral-type power MOSFET, high breakdown voltage is achieved with suppressing to increase a cell pitch, and a feedback capacity and an ON resistance are decreased. An n? type silicon region having a high resistance to be a region of maintaining a breakdown voltage is vertically provided with respect to a main surface of an n+ type silicon substrate, and the n? type silicon region having the high resistance is connected to the n+ type silicon substrate. Also, a conductive substance is filled through an insulating substance inside a trench formed to reach the n+ type silicon substrate from the main surface of the n+ type silicon substrate so as to contact with the n? type silicon region having the high resistance, and the conductive substance is electrically connected to a source electrode.
    Type: Application
    Filed: June 18, 2010
    Publication date: December 30, 2010
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Takayuki HASHIMOTO, Takashi HIRAO, Noboru AKIYAMA
  • Patent number: 7852651
    Abstract: The object of the present invention is to reduce parasitic inductance of a main circuit in a power supply circuit. The present invention provides a non-insulated DC-DC converter having a circuit in which a power MOS•FET for a high-side switch and a power MOS•FET for a low-side switch are connected in series. In the non-insulated DC-DC converter, the power MOS•FET for the high-side switch is formed by a p channel vertical MOS•FET, and the power MOS•FET for the low-side switch is formed by an n channel vertical MOS•FET. Thus, a semiconductor chip formed with the power MOS•FET for the high-side switch and a semiconductor chip formed with the power MOS•FET for the low-side switch are mounted over the same die pad and electrically connected to each other through the die pad.
    Type: Grant
    Filed: April 28, 2009
    Date of Patent: December 14, 2010
    Assignee: Renesas Electronics Corporation
    Inventors: Masaki Shiraishi, Noboru Akiyama, Tomoaki Uno, Nobuyoshi Matsuura
  • Publication number: 20100289982
    Abstract: The semiconductor device is included in the LED driving circuit (current regulator) of driving the LED array (with series-connected number m×parallel-connected number n), and is formed of a plurality (n pieces) of LED driving devices of controlling a current (constant-current driving) flowing in each string. A vertical semiconductor device, for example, a vertical MOSFET is used as the LED driving device. Both of a main device functioning as a constant-current driving device and a subsidiary device functioning as a circuit-breaking switch during dimming are formed inside a chip of the device, which are formed of the vertical semiconductor devices. In a first surface of the device, each source region of the main device and the subsidiary device is formed so as to be insulated from each other through an isolation region.
    Type: Application
    Filed: May 13, 2010
    Publication date: November 18, 2010
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Noboru AKIYAMA, Takayuki HASHIMOTO, Takashi HIRAO, Nobuyoshi MATSUURA, Hideo ISHII
  • Patent number: 7821243
    Abstract: In a non-isolated DC/DC converter, a reference potential for a low-side pre-driver which drives a gate of a low-side MOSFET is applied from a portion except for a main circuit passing through a high-side MOSFET and the low-side MOSFET so that a parasitic inductance between a source of the low-side MOSFET and the pre-driver is increased without increasing the sum of parasitic inductances in the main circuit and negative potential driving of the gate of the low-side MOSFET can be performed and a self turn-on phenomenon can be prevented without adding any member and changing drive system.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: October 26, 2010
    Assignee: Renesas Electronics Corp.
    Inventors: Masaki Shiraishi, Takayuki Hashimoto, Noboru Akiyama
  • Publication number: 20100253306
    Abstract: In a non-isolated DC/DC converter, a reference potential for a low-side pre-driver which drives a gate of a low-side MOSFET is applied from a portion except for a main circuit passing through a high-side MOSFET and the low-side MOSFET so that a parasitic inductance between a source of the low-side MOSFET and the pre-driver is increased without increasing the sum of parasitic inductances in the main circuit and negative potential driving of the gate of the low-side MOSFET can be performed and a self turn-on phenomenon can be prevented without adding any member and changing drive system.
    Type: Application
    Filed: June 18, 2010
    Publication date: October 7, 2010
    Inventors: Masaki Shiraishi, Takayuki Hashimoto, Noboru Akiyama
  • Patent number: 7770403
    Abstract: An air conditioning system is arranged to use a power line for communication. The air conditioning system includes one or more indoor units, one or more outdoor units, and a system controller for controlling the indoor units or outdoor units and executes communications between the indoor units and the outdoor units as overlapping a signal on the power line for supplying electric power. The outdoor units are connected with the system controller through a leased communication line. The indoor unit provides a power line communication device being connected with the power line. The outdoor unit provides a leased communication device being connected with the leased communication line. A bridge is also provided for connecting the leased communication line and the power line. The control information is exchanged mutually between the indoor units, the outdoor units and the system controller through the power line.
    Type: Grant
    Filed: February 10, 2009
    Date of Patent: August 10, 2010
    Assignee: Hitachi Appliances, Inc.
    Inventors: Yasuyuki Kojima, Noboru Akiyama, Takeshi Onaka, Tatsumi Yamauchi, Koichi Taniguchi, Koichi Tokushige, Noriyuki Bunkou, Keiji Sato
  • Publication number: 20100177127
    Abstract: An LED driving circuit driving an LED array includes: n constant-current driving elements having a vertical structure, each of which is connected to each of LED strings in series and drives the LED string with a constant current; n constant-current control circuits controlling on voltages of the constant-current driving elements so that currents flowing to the LED strings become constant currents; a lowest-voltage detecting circuit to which terminal voltages of the constant-current driving elements on an LED string side are inputted, the lowest-voltage detecting circuit selecting a lowest voltage from among the terminal voltages and outputting a command signal based on difference between the lowest voltage and a predetermined set voltage; and a power-supply control circuit controlling a voltage applied to the LED array to a voltage lower than an initial set voltage based on the command signal.
    Type: Application
    Filed: January 7, 2010
    Publication date: July 15, 2010
    Applicant: RENESAS TECHNOLOGY CORP.,
    Inventors: Noboru AKIYAMA, Takayuki HASHIMOTO, Takashi HIRAO, Nobuyoshi MATSUURA
  • Publication number: 20100176430
    Abstract: The present invention provides a technology for reducing the parasitic inductance of the main circuit of a power source unit.
    Type: Application
    Filed: March 10, 2010
    Publication date: July 15, 2010
    Applicant: Renesas Technology Corp.
    Inventors: Takayuki Hashimoto, Noboru Akiyama, Masaki Shiraishi, Tetsuya Kawashima
  • Patent number: 7687885
    Abstract: The present invention provides a technology for reducing the parasitic inductance of the main circuit of a power source unit. In a non-insulated DC-DC converter having a circuit in which a power MOSFET for high side switch and a power MOSFET for low side switch are connected in series, the power MOSFET for high side switch and the power MOSFET for low side switch are formed of n-channel vertical MOSFETS, and a source electrode of the power MOSFET for high side switch and a drain electrode of the power MOSFET for low side switch are electrically connected via the same die pad.
    Type: Grant
    Filed: May 30, 2007
    Date of Patent: March 30, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Takayuki Hashimoto, Noboru Akiyama, Masaki Shiraishi, Tetsuya Kawashima
  • Publication number: 20100017636
    Abstract: In a power supply system having: a processor 1; a power supply controller 31 and a VR 35 to be a switching regulator for supplying power to the processor; a voltage command generator 11 and a clock command generator 16 for varying an operation voltage and a clock frequency of a processor core of the processor; and a battery 34 to be an input direct-current voltage source of the switching regulator, the clock frequency of the power supply controller 31 is lowered when the computation amount of the processor 1 is small. Accordingly, the loss of the power supply controller 31 is reduced, thereby extending the battery life in the electronic device.
    Type: Application
    Filed: November 21, 2007
    Publication date: January 21, 2010
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Takayuki Hashimoto, Masaki Shiraishi, Noboru Akiyama
  • Publication number: 20100001790
    Abstract: In a semiconductor device, a high-side driver is arranged in a region closer to a periphery of a semiconductor substrate than a high-side switch, and a low-side driver is arranged in a region closer to the periphery of the semiconductor substrate than the low-side switch. By this means, a path from a positive terminal of an input capacitor to a negative terminal of the input capacitor via the high-side switch and the low-side switch is short, a path from a positive terminal of a drive capacitor to a negative terminal of the drive capacitor via the low-side driver is short, and a path from a positive terminal of a boot strap capacitor to a negative terminal of the boot strap capacitor via the high-side driver is short, and therefore, the parasitic inductance can be reduced, and the conversion efficiency can be improved.
    Type: Application
    Filed: June 12, 2009
    Publication date: January 7, 2010
    Inventors: Takayuki HASHIMOTO, Takashi Hirao, Noboru Akiyama
  • Patent number: 7598605
    Abstract: A primary side circuit and a secondary side circuit are provided on first and second semiconductor substrates, respectively. A first capacitive insulator on the first substrate electrically insulates and isolates between the primary and secondary side circuits while permitting signal transmission between these circuits. A second capacitive insulator on the second semiconductor substrate electrically isolates the primary and secondary side circuit while permitting signal transmission therebetween. First and second frames are provided for input and output of signals to and from the primary and secondary side circuits. External electrodes of the first and second capacitive insulators are connected together by a third lead frame via a conductive adhesive body including more than one solder ball. The first and second substrates and the lead frames are sealed by a dielectric resin.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: October 6, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Noboru Akiyama, Minehiro Nemoto, Seigou Yukutake, Yasuyuki Kojima, Kazuyuki Kamegaki
  • Publication number: 20090243575
    Abstract: A semiconductor device for control applied to a constant-voltage power supply device includes a digital-analog converter circuit which outputs a reference voltage corresponding to a value of a first register with taking an output voltage of a reference voltage source as a criterial reference voltage, and generates a control signal for driving a power semiconductor device based on an output voltage of an error amplifier which differentially amplifies a feedback voltage obtained by resistive-dividing on an output voltage of the constant-voltage power supply device and the reference voltage. An analog-digital converter circuit which converts the feedback voltage to a digital value with taking the output voltage of the constant-voltage power supply device as a reference voltage is provided, and based on the output, a value of a first register is corrected so as to offset an effect of an error in voltage dividing ratio of a voltage dividing resistor circuit.
    Type: Application
    Filed: February 19, 2009
    Publication date: October 1, 2009
    Inventors: Noboru AKIYAMA, Takayuki Hashimoto, Takashi Hirao, Koji Tateno, Takuya Ishigaki