Abstract: Disclosed is a transmission power control method which enables communications between a base station and a terminal station to be always performed at a high transfer rate by always assuring an uplink communication path between a base station which can transfer a downlink signal most efficiently and a terminal station. Each of terminal stations 111 to 119 selects a base station which can receive a downlink radio wave with the highest power, and transmits a code for identifying the base station on an uplink signal. When the received power of the uplink radio waves transmitted from the terminal station which has transmitted the code identifying the own station is higher than the threshold value, each of base stations 501 to 503 transmits a control signal for decreasing the power to the terminal station.

Abstract: An on-chip multiprocessor having a chip layout for efficient multiprocessor control, wherein multiple processors and shared portions such as shared caches are symmetric with respect to a desired linear axis and a multiprocessor controller is located in the area containing said linear axis. This makes the distances between the processors and the controller equal and shorter, and also decreases differences in the distance between the controller and shared portions, thereby permitting higher speed processing of signals among these.

Abstract: The disclosed invention makes mobile terminals physically impossible to use in specific spaces without using radio waves of so high intensity as to affect medical devices and without requiring telephone companies that operate wireless communications systems (WCS) to take special measures. Cooperation of a telephone company on the implementation of making mobile terminals physically impossible to use in specific spaces makes mobile terminals provided by the telephone company easy to use. Pseudo signals of downlink pilot signal in WCS are emitted off the pilot timing in specific spaces. Uplink channel radio waves in cooperative telephone compannies' WCS are relayed and communication path is disconnected if the uplink channel radio waves are for communication of an attribute banned in the space. Communication path can be disconnected without increasing the intensity of radio waves so high.

Abstract: There is disclosed a network telephone system which registers subscriber information necessary to monitor a call upon a request for call transfer by a first subscriber who has made dial-up connection, notifies the first subscriber that there is an incoming call from a second subscriber, and makes a call setup for voice in accordance with an instruction from the first subscriber.

Abstract: The present invention relates to a PLL circuit and a voltage controlled oscillator wherein a clock signal jitter caused when the supply voltage fluctuates of which is small can be supplied, and the voltage controlled oscillator is provided with a MOS transistor to one end of which a first power source (Vss) is connected and to the gate electrode of which a control signal for controlling the oscillation frequency is input, an oscillator connected between the other end of the MOS transistor and a second power source (Vdd) and a capacitative element connected to the oscillator in parallel and is further provided with additive control means for minutely controlling the oscillation frequency.

Abstract: The intermittent coating apparatus which includes a nozzle 1 which applies a paint 6 to a base material, a feeding side two-way valve 10 which repeats feeding of the paint 6 to the nozzle 1 and stop of the feeding, a return side two-way valve which 11 repeats discharge of the paint 6 to a return side and stop of the discharge, a paint flow path 12, means to feed the paint 6 into the flow path 12, and paint returning means 5 which repeats suction and return of the paint 6 out of and into the nozzle 1, and is characterized in that switching of the feeding side two-way valve 10 is carried out earlier than that of the return side two-way valve 11 within a range not shorter than 5 msec and not longer than 100 msec at least at a coating start time.

Abstract: Disclosed is a transmission power control method which enables communications between a base station and a terminal station to be always performed at a high transfer rate by always assuring an uplink communication path between a base station which can transfer a downlink signal most efficiently and a terminal station. Each of terminal stations 111 to 119 selects a base station which can receive a downlink radio wave with the highest power, and transmits a code for identifying the base station on an uplink signal. When the received power of the uplink radio waves transmitted from the terminal station which has transmitted the code identifying the own station is higher than the threshold value, each of base stations 501 to 503 transmits a control signal for decreasing the power to the terminal station.

Abstract: A clocked logic gate circuit is constituted so that a switch unit is constituted by a logic block and a reference MOS transistor, the source of the reference MOS transistor is connected to one output of the logic block, the gate of the reference MOS transistor is connected to the other output of the logic block, and MOS transistors (input transistors) constituting the logic block are connected in parallel. With this arrangement, complementary inputs are not required and a driving MOS transistor and an input transistor (or a driving MOS transistor and a reference MOS transistor) can be connected in series. As a result, a circuit is obtained which is simpler than the double rail logic in constitution is facilitated and can be operated at a higher speed than a CMOS logic circuit and a path transistor logic circuit.

Abstract: Disclosed herein is a dynamic type circuit which transmits a signal between relatively long-distant circuit blocks lying within a semiconductor integrated circuit chip. A whole signal path thereof comprises a plurality of sections. A section formed by a first type of signal line, which is precharged to a high level and to which a decision as to whether it is driven to a low level according to a signal inputted from a preceding section or it is left in floating state, is made, and a section formed by a second type of signal line, which is precharged to a low level in reverse and to which a decision as to whether it is driven to a high level according to a signal inputted from a preceding section or it is left in a floating state, is made, exist in alternate shifts. The respective sections are respectively connected to preceding-stage sections through MOS transistors for driving signal lines for the sections.

Abstract: A clocked logic gate circuit is constituted so that a switch unit is constituted by a logic block and a reference MOS transistor, the source of the reference MOS transistor is connected to one output of the logic block, the gate of the reference MOS transistor is connected to the other output of the logic block, and MOS transistors (input transistors) constituting the logic block are connected in parallel. With this arrangement, complementary inputs are not required and a driving MOS transistor and an input transistor (or a driving MOS transistor and a reference MOS transistor) can be connected in series. As a result, a circuit is obtained which is simpler than the double rail logic in constitution is facilitated and can be operated at a higher speed than a CMOS logic circuit and a path transistor logic circuit.

Abstract: A clocked logic gate circuit is constituted so that a switch unit is constituted by a logic block and a reference MOS transistor, the source of the reference MOS transistor is connected to one output of the logic block, the gate of the reference MOS transistor is connected to the other output of the logic block, and MOS transistors (input transistors) constituting the logic block are connected in parallel. With this arrangement, complementary inputs are not required and a driving MOS transistor and an input transistor (or a driving MOS transistor and a reference MOS transistor) can be connected in series. As a result, a circuit is obtained which is simpler than the double rail logic in constitution is facilitated and can be operated at a higher speed than a CMOS logic circuit and a path transistor logic circuit.

Abstract: In a dynamic logic circuit, a signal delay time between a low-to-high transition of an input signal and a low-to-high transition of an output signal is reduced, a through current is decreased and a time required for the precharge is reduced. In the dynamic logic circuit a P-channel type MOS transistor (PMOS) has its source electrode connected with a power supply on the side of a high voltage potential Vdd. Its gate electrode receives a clock signal Cs. A logic portion includes N-channel type MOS transistors (NMOS) connected between a drain electrode of the PMOS and a power supply on the side of a low voltage potential Vss. An NMOS is provided between an input signal connected with a NMOS closest to the Vss in the NMOSs and the Vss. A reverse signal of the clock signal Cs is connected with a gate electrode of the NMOS. An input signal is forced to change to a low level at the time of the precharge, thereby a through current is decreased and a time required for the precharge is reduced.

Abstract: An IC testing apparatus 1 for performing a test by applying at least a low temperature stress to ICs to be tested comprising a refrigerant cycle 210 wherein at least a compressor 211, condenser 212, expansion valve 214 and evaporator 215 are connected in this order, and a cold air applying line 220 having a blower 223 for supplying heat exchanged cold air by the evaporator 215 to the ICs to be tested.

Abstract: Disclosed herein is a dynamic type circuit which transmits a signal between relatively long-distant circuit blocks lying within a semiconductor integrated circuit chip. A whole signal path thereof comprises a plurality of sections. A section formed by a first type of signal line, which is precharged to a high level and to which a decision as to whether it is driven to a low level according to a signal inputted from a preceding section or it is left in floating state, is made, and a section formed by a second type of signal line, which is precharged to a low level in reverse and to which a decision as to whether it is driven to a high level according to a signal inputted from a preceding section or it is left in a floating state, is made, exist in alternate shifts. The respective sections are respectively connected to preceding-stage sections through MOS transistors for driving signal lines for the sections.

Abstract: A lubricant composition for a refrigerating machine employing a HFC type refrigerant containing at least one selected from the group consisting of HFC-32, HFC-125 and HFC-134a, which comprises a base oil of an ester formed from a dihydric or higher polyol as an alcohol and a monobasic aliphatic acid, alone or as a mixture thereof; and additives of, based on the total amount, 1) not less than 0.01 vol % and less than 1.0 vol % of a phosphate, 2) from 0.01 to 1.0 vol % of at least one of an alkylphosphorothionate and an arylphosphorothionate and 3) from 0.01 to 1.0 vol % of an epoxy compound.

Abstract: A clocked logic gate circuit is constituted so that a switch unit is constituted by a logic block and a reference MOS transistor, the source of the reference MOS transistor is connected to one output of the logic block, the gate of the reference MOS transistor is connected to the other output of the logic block, and MOS transistors (input transistors) constituting the logic block are connected in parallel. With this arrangement, complementary inputs are not required and a driving MOS transistor and an input transistor (or a driving MOS transistor and a reference MOS transistor) can be connected in series. As a result, a circuit is obtained which is simpler than the double rail logic in constitution is facilitated and can be operated at a higher speed than a CMOS logic circuit and a path transistor logic circuit.

Abstract: A clocked logic gate circuit is constituted so that a switch unit is constituted by a logic block and a reference MOS transistor, the source of the reference MOS transistor is connected to one output of the logic block, the gate of the reference MOS transistor is connected to the other output of the logic block, and MOS transistors (input transistors) constituting the logic block are connected in parallel. With this arrangement, complementary inputs are not required and a driving MOS transistor and an input transistor (or a driving MOS transistor and a reference MOS transistor) can be connected in series. As a result, a circuit is obtained which is simpler than the double rail logic in constitution is facilitated and can be operated at a higher speed than a CMOS logic circuit and a path transistor logic circuit.

Abstract: A refrigerant-circulating system which comprises a refrigeration cycle comprising a refrigerant compressor, a condenser, an expansion mechanism and an evaporator to form a refrigerant circuit and employing a refrigerant which contains no chlorine, wherein an aromatic polyether oil having as a base oil structure a benzene ring having an ether bond is employed as a refrigerator oil.

Abstract: A logic circuit for use as a selector having multiple inputs and high operation speed. The logic circuit includes a first FET having a first electrode connected to a first power supply, a second electrode connected to an output terminal and a third electrode connected to an intermediate control node, and a plurality of logic blocks parallelly connected between the second power supply and the output terminal. Each logic block includes second and third FETs being of a conductivity type opposite to that of the first FET and connected in series between the output terminal and a second power supply. Each logic block also includes a fourth FET being of the same conductivity type as the second and third FETs and having a third electrode connected to the third electrode of the second FET, a first electrode connected to the third electrode of the third FET and a second electrode connected to the intermediate control node.

Abstract: In transmitting and receiving signals between a plurality of units in a information processing system, signals can be transmitted and received between circuits operated by asynchronous clocks which are the same in period (frequency) but not necessarily to be the same in phase, thereby permitting the information processing system to operate with a shorter clock period. A delay circuit arranged in the communication path is so controllable that the data sent out in synchronism with the clock signal of a transmitting unit is correctly retrieved in synchronism with the clock signal of a receiving unit. Further, data having a predetermined simple pattern is sent out in synchronism with the clock signal of the transmitting unit, and it is decided whether the data has been correctly received by the receiving unit. The delay circuit is automatically controlled by use of the result of decision.