Patents by Inventor Noboru Masuda

Noboru Masuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5729550
    Abstract: In transmitting and receiving signals between a plurality of units in a information processing system, signals can be transmitted and received between circuits operated by asynchronous clocks which are the same in period (frequency) but not necessarily to be the same in phase, thereby permitting the information processing system to operate with a shorter clock period. A delay circuit arranged in the communication path is so controllable that the data sent out in synchronism with the clock signal of a transmitting unit is correctly retrieved in synchronism with the clock signal of a receiving unit. Further, data having a predetermined simple pattern is sent out in synchronism with the clock signal of the transmitting unit, and it is decided whether the data has been correctly received by the receiving unit. The delay circuit is automatically controlled by use of the result of decision.
    Type: Grant
    Filed: March 20, 1996
    Date of Patent: March 17, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Kazunori Nakajima, Noboru Masuda, Tadaaki Isobe, Masamori Kashiyama, Bunichi Fujita, Masakazu Yamamoto
  • Patent number: 5653909
    Abstract: A refrigerating machine oil composition suitable for a compressor using a hydrofluorocarbon as a refrigerant, which comprises 100 parts by weight of a polyol ester as a base oil, from 7.0 to 15.0 parts by weight of a phosphate, and from 0.2 to 3.0 parts by weight in total of a 1,2-epoxyalkane and/or a vinylcyclohexene dioxide. The use of the refrigerating machine oil composition improves wear resistance of sliding portions of compressors and is free from the formation of sludges derived from the polyol ester used as a base oil of the oil composition. A rotary compressor using the oil composition is also disclosed.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: August 5, 1997
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Oil Company, Limited
    Inventors: Masayoshi Muraki, Yukiharu Beppu, Shozaburo Konishi, Susumu Kawaguchi, Noboru Masuda, Sou Suzuki
  • Patent number: 5604840
    Abstract: An information processing apparatus is composed of an input layer, a hidden layer and an output layer, and performs a computation in terms of neuron models. In the information processing apparatus, a forward network comprising the input layer, the hidden layer and the output layer executes a computation for externally input data to determine the values of outputs therefrom, and a backward network comprising the output layer and the hidden layer executes computation for output values expected for given inputs to determine learning signal values. The information processing apparatus transfers the output values and learning values between the forward network and the backward network to modify the synapse weights of the neuron models.
    Type: Grant
    Filed: March 29, 1993
    Date of Patent: February 18, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Mitsuo Asai, Noboru Masuda, Moritoshi Yasunaga, Masayoshi Yagyu, Minoru Yamada, Katsunari Shibata
  • Patent number: 5576997
    Abstract: A data processing system having a logic LSI, a plurality of memory LSIs and a circuit which eliminates delays in the time at which data read out form the memory LSIs reach the logic LSI. The circuit includes variable delay circuits for delaying the data signals read out of the memory LSIs. A control circuit start monitors the time when the data read out of the individual memory LSIs arrive at flip-flops which output the data to the logic LSI. The delay times in the variable delay circuits are controlled by the control circuit for the individual memory LSIs so that the times the data read out from the memory LSIs reach the logic LSI may coincide with a predetermined standard time. Thus, the read data from the individual memory LSIs are caused to reach the flip-flops simultaneously.
    Type: Grant
    Filed: September 20, 1994
    Date of Patent: November 19, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Noboru Masuda, Kazunori Nakajima, Hideo Maejima
  • Patent number: 5531080
    Abstract: A refrigerant circulating system that uses a highly polar refrigerant, as typified by a hydrofluorocarbon-based one, and a refrigerating oil that has slight solubility with a liquid refrigerant on the condensation side. Also, a refrigerant circulating cycle that uses a highly polar refrigerant, as typified by a hydrofluorocarbon-based one, and a refrigerating oil that has a slight solubility with a liquid refrigerant and which has a greater specific gravity than the liquid refrigerant. Thereby, it provides a high electrical insulation and moisture resistance, good oil return to the compressor, and high reliability.
    Type: Grant
    Filed: July 12, 1994
    Date of Patent: July 2, 1996
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takuho Hirahara, Susumu Kawaguchi, Tatsuaki Shimizu, Katsuyuki Kawasaki, Noboru Masuda, Shinobu Ogasawara, Hiroshige Konishi, Hitoshi Maruyama, Yoshihiro Sumida, Akemi Ueyama, Satoru Toyama, Sou Suzuki, Yasushi Akahori
  • Patent number: 5512822
    Abstract: A magnetic sensor includes a member having a magnetic contour anisotropy. A counterpart yoke is disposed above a magnet. The thickness of the counterpart yoke is equal to or slightly smaller than the resolution. The counterpart yoke has a magnetic contour anisotropy for restraining the divergence of the magnetic flux from the magnet. The resolution can be prevented from being reduced depending on the distance between a medium and a magnetic sensing element. At the same time, the magnet can be miniaturized.
    Type: Grant
    Filed: January 4, 1995
    Date of Patent: April 30, 1996
    Assignee: Murata Mfg. Co., Ltd.
    Inventor: Noboru Masuda
  • Patent number: 5497263
    Abstract: A variable delay circuit including delay devices each having a plurality of delay units connected successively, only some of the delay units of the delay devices being connected to a signal transmission line, wherein a delay time is controlled by activating or inactivating the plurality of delay units according to control signals applied to control input terminals provided respectively for said plurality of delay units.
    Type: Grant
    Filed: September 7, 1993
    Date of Patent: March 5, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Noboru Masuda, Kazumichi Yamamoto, Kazunori Nakajima, Toshihiro Okabe, Akira Yamagiwa, Mikio Yamagishi, Kazuo Koide, Bunichi Fujita, Seiichi Kawashima
  • Patent number: 5434453
    Abstract: A semiconductor integrated circuit device includes a plurality of integrated circuit chips and a large-sized integrated circuit element on which the plurality of integrated circuit chips are mounted. The large-sized integrated circuit element includes a logic circuit for electrically interconnecting the integrated circuit chips mounted on it. The logic circuit provided within the large-sized integrated circuit element includes a control circuit for controlling a connection relation between the integrated circuit chips mounted on the large-sized integrated circuit element. Further, the logic circuit includes buffer or latch circuits for relaying signals transmitted between the integrated circuit chips.
    Type: Grant
    Filed: April 22, 1992
    Date of Patent: July 18, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Kazumichi Yamamoto, Keiichirou Nakanishi, Moritoshi Yasunaga, Tatsuya Saitoh, Katsunari Shibata, Minoru Yamada, Noboru Masuda
  • Patent number: 5430397
    Abstract: An intra-LSI clock distribution circuit which includes a main distribution circuit, a plurality of intra-block clock distribution circuitries, feedback wires provided in association with each of blocks and each connected to one of plural block-based clock signal wires within the associated block and the intra-block distribution circuitry of the associated block for feeding back the intra-block clock signal distributed to a given one of circuit elements connected to the intra-block clock signal wires to the intra-block clock distribution circuitry of that block.
    Type: Grant
    Filed: January 26, 1994
    Date of Patent: July 4, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Hiroyuki Itoh, Noboru Masuda, Hideo Maejima, Tadahiko Nishimukai
  • Patent number: 5419144
    Abstract: A method of assembling a closed loop refrigerating air conditioning system using a hydrofluorocarbon refrigerant by applying a first oil which is insoluble with the hydrocarbon refrigerant to components of a compressor, and storing the insoluble oil within the housing of the compressor in a single or mixed state.
    Type: Grant
    Filed: June 13, 1994
    Date of Patent: May 30, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Susumu Kawaguchi, Tatsuaki Shimizu, Hiroshige Konishi, Hitoshi Maruyama, Noboru Masuda, Shinobu Ogasawara, Yoshihiro Sumida, Satoru Toyama
  • Patent number: 5355695
    Abstract: A refrigeration device comprising a compressor, a condenser, an evaporator, an accumulator and a refrigerant is described. Lubricating oil present in the compressor is chosen so as to be insoluble with the refrigerant, and a particular accumulator design is described to ensure return of oil back to the compressor.
    Type: Grant
    Filed: November 30, 1992
    Date of Patent: October 18, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Susumu Kawaguchi, Tatsuaki Shimizu, Hiroshige Konishi, Hitoshi Maruyama, Noboru Masuda, Shinobu Ogasawara, Yoshihiro Sumida, Satoru Toyama
  • Patent number: 5325067
    Abstract: It is an object of the present invention to prevent variations in sensitivity of the sensor circuits of the respective channels by equalizing the power of oscillation frequency signals to be distributed/supplied from one oscillation circuit to the sensor circuits of the respective channels. Multi-channel sensor circuits are arranged with a common oscillation circuit. A high-impedance conversion circuit is connected to the output terminal of the oscillation circuit. A first impedance matching circuit for performing impedance matching of resonance circuits of the respective channels with reference to the oscillation circuit is arranged on the output side of the high-impedance conversion circuit. Second impedance matching circuits for performing impedance matching of the oscillation circuit with reference to the resonance circuits are connected at the input terminals of the resonance circuits of the respective channels.
    Type: Grant
    Filed: May 25, 1993
    Date of Patent: June 28, 1994
    Assignee: Murata Mfg. Co., Ltd.
    Inventors: Noboru Masuda, Tetsuo Oosawa, Yasutaka Fujii
  • Patent number: 5278457
    Abstract: The invention relates to method and apparatus for adjusting a clock signal which is supplied to an electronic apparatus. After the turn-on of a power source of the electronic apparatus, it is detected that a temperature of at least a part of devices in the electronic apparatus substantially reaches a saturation state. When the temperature of the device reaches the saturation state, a phase adjustment of the clock signal of the electronic apparatus is executed. After completion of the phase adjustment of the clock signal, its adjusting state is fixed.
    Type: Grant
    Filed: June 19, 1992
    Date of Patent: January 11, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Yuzuru Fujita, Seiichi Kawashima, Bunichi Fujita, Sakoh Ishikawa, Noboru Masuda
  • Patent number: 5231359
    Abstract: A ceramic resonance type electrostatic sensor apparatus with an oscillator at a fixed frequency including a first ceramic resonator which has a fixed resonance frequency, a detecting unit for detecting a capacitance between the detecting unit and an object to be detected, a resonating circuit including a second ceramic resonator and having a resonance point which varies with the small change in capacitance detected by the detecting unit, a high impedance circuit connected between the oscillator and the resonating circuit, and a high impedance circuit connected between the resonating circuit and the detecting circuit.
    Type: Grant
    Filed: May 18, 1990
    Date of Patent: July 27, 1993
    Assignee: Murata Mfg. Co., Ltd.
    Inventors: Noboru Masuda, Tetsuo Ohsawa, Takashi Sugimura
  • Patent number: 5214743
    Abstract: An information processing apparatus which includes an input layer, a hidden layer and an output layer, and performs a computation in terms of models of neurons. A forward network, having the input layer, the hidden layer and the output layer, executes a computation for externally input data to determine the values of outputs therefrom, and a backward network, having the output layer and the hidden layer, executes computation for output values expected for given inputs to determine learning signal values. The information processing apparatus transfers the output values and learning values between the forward network and the backward network to modify the synapse weights of the neuron models.
    Type: Grant
    Filed: October 24, 1990
    Date of Patent: May 25, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Mitsuo Asai, Noboru Masuda, Moritoshi Yasunaga, Masayoshi Yagyu, Minoru Yamada, Katsunari Shibata
  • Patent number: 5198777
    Abstract: Apparatus for detecting thickness which includes an electrode detecting unit including a ground electrode and a detecting electrode. The electrodes oppose each other along a paper path. An oscillating circuit provides an oscillation frequency signal. A resonant circuit, having a resonator independent of the oscillating circuit, has a resonance point which changes in accordance with a change in electro-static capacitance corresponding to a change in paper thickness detected by the electrode detecting unit. A resonant circuit outputs a detection signal corresponding to the change in resonance point. By analyzing this detecting signal, a state of two sheets of paper passing through the path is detected as a change in paper thickness.
    Type: Grant
    Filed: February 12, 1991
    Date of Patent: March 30, 1993
    Assignee: Murata Mfg. Co., Ltd.
    Inventors: Noboru Masuda, Tetsuo Oosawa, Yasutaka Fujii
  • Patent number: 5184027
    Abstract: A clock signal supply system provides for automatic accurate phase adjustment of clock signals. The system includes an oscillator that produces clock signals and a reference generator that generates a reference signal that has a predetermined relationship with respect to the clock signals produced by the oscillator. At each location where the clock signal is to be received, an adjusting circuit is provided to adjust the phase of the received clock signals. Such an adjusting circuit may include a variable delay circuit which receives the clock signal and produces an output which is constituted by the clock signal having a varied delay, to the remainder of the attached circuits. Further, the output of the variable delay is fed back to a phase difference detection circuit. The reference signal is second input to the phase difference detection circuit.
    Type: Grant
    Filed: April 22, 1991
    Date of Patent: February 2, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Noboru Masuda, Ryotaro Kamikawai, Masayoshi Yagyu, Masakazu Yamamoto, Hiroyuki Itoh, Tatsuya Saito
  • Patent number: 5165010
    Abstract: An information processing system includes a plurality of functional blocks (neurons) and a data bus for transmitting in common the outputs of the individual functional blocks (neurons). Data transaction among the functional blocks (neurons) is performed through the data bus on the time-division basis. For preventing the outputs from conflicting or competition, addresses are assigned to the individual blocks (neurons), respectively, so that only the functional blocks (neuron) having the own address designated by the address signal supplied through an address bus outputs data signal onto the data bus, while the other functional blocks (neurons) receive the information on the data bus as the signal originating in the functional block whose address is designated at that time point. The addresses are sequentially changed. During a round of the address signals, data are transmitted from given functional blocks (neurons) to other given functional blocks (neurons).
    Type: Grant
    Filed: January 4, 1990
    Date of Patent: November 17, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Noboru Masuda, Moritoshi Yasunaga, Minoru Yamada, Akira Masaki, Mitsuo Asai, Yuzo Hirai, Masayoshi Yagyu, Takehisa Hayashi, Toshio Doi, Kenichi Ishibashi
  • Patent number: 5150068
    Abstract: The present invention provides a clock signal supply method and system. A reference signal and a synchronizing signal are generated, as well as a clock signal, at a clock signal generating source end. Both the reference signal and the synchronizing signal have a period longer than that of the clock signal. The clock signal at a clock signal destination end is frequency divided in synchronism with the synchronizing signal to provide a sample to be compared with the reference signal. The resultant frequency-divided signal is compared with the reference signal in phase. A delay control is made for the clock signal in accordance with the result of the comparison to adjust the phase of the clock signal at the signal destinations.
    Type: Grant
    Filed: August 9, 1989
    Date of Patent: September 22, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Seiichi Kawashima, Noboru Masuda, Shuichi Ishii, Bunichi Fujita
  • Patent number: 5132752
    Abstract: A field effect transistor formed on a semi-insulator or compound semiconductor substrate comprises a first semiconductor layer forming a source region, a drain region and a channel layer, and a second semiconductor layer having a reverse conduction type to that of the first semiconductor layer. The second semiconductor layer is doped so that it will be totally depleted. Therefore, a portion of the second semiconductor layer adjacent to the substrate will remain conductive. The field effect transistor with this structure prevents the short channel effect and the soft error due to .alpha.-particles. A threshold voltage control arrangement is also provided using the feature of a control electrode coupled to the second semiconductor layer and a feedback arrangement.
    Type: Grant
    Filed: February 22, 1991
    Date of Patent: July 21, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Yasunari Umemoto, Nobuo Kotera, Kiichi Ueyanagi, Norikazu Hashimoto, Nobutoshi Matsunaga, Yasuo Wada, Shoji Shukuri, Noboru Masuda, Takehisa Hayashi, Hirotoshi Tanaka