Patents by Inventor Nobutake Tsuyuno

Nobutake Tsuyuno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090086437
    Abstract: In an electronic control device that includes two or more kinds of lead-insertion-type parts, including at least a coil and a capacitor, the parts are installed on a support that has a wiring, a terminal structure and mechanically fixing portions; the leads of the above parts are respectively inserted in and electrically connected to holes formed in the wiring portion of the support; the parts and the support are fixed to each other with an adhesion material for fixation; the upper surfaces of the parts are attached to a metallic chasis with a thermally conductive material of a low elasticity modulus interposed in between; the mechanically fixing portions of the support are fixed to the metallic chasis; and the terminal structure of the support is electrically connected to a circuit board that mounts at least a controlling element.
    Type: Application
    Filed: August 13, 2008
    Publication date: April 2, 2009
    Inventors: Nobutake Tsuyuno, Hideto Yoshinari, Hiroshi Hozoji, Masahiko Asano, Masahide Harada, Shinya Kawakita
  • Publication number: 20080294324
    Abstract: An engine control unit for controlling an automobile engine, which is equipped with a booster circuit for boosting the voltage of battery power source, an injector driving circuit for driving an injector by making use of a boosted high voltage, and a microcomputer for controlling the engine; wherein the engine control unit is featured in that an LC module mounted with a booster coil constituting the booster circuit and with an electrolytic capacitor, a power module mounted with a rectifying device constituting the booster circuit and the injector driving circuit and with a switching device, and a control circuit board mounted with the microcomputer and with a connector acting as an interface for an external member of the engine control unit are laminated each other.
    Type: Application
    Filed: May 23, 2008
    Publication date: November 27, 2008
    Applicant: Hitachi, Ltd.
    Inventors: Hideto Yoshinari, Yujiro Kaneko, Masahiko Asano, Nobutake Tsuyuno, Takehide Yokozuka
  • Publication number: 20080106160
    Abstract: A power module comprises a heat radiation layer having the first main surface and the second main surface of reverse side opposed to the first main surface, an insulation layer disposed on the first main surface of a radiation layer, a wiring potion for current circuit disposed on the insulation layer and a plurality of switching element disposed on the insulation layer and electrically connected to the wiring portion of current circuit. A plurality of external terminals are electrically connected to the wiring portions of current circuit. Furthermore, the module has a resin sealing all of the insulation layer, a wiring portion for current circuit, switching elements and the first main surface of the radiation layer, and a resin sealing a portion of the second main surface of the radiation layer with the resin.
    Type: Application
    Filed: November 7, 2007
    Publication date: May 8, 2008
    Applicant: Hitachi, Ltd.
    Inventors: Hideto Yoshinari, Yujiro Kaneko, Masahide Harada, Nobutake Tsuyuno, Shinichi Fujiwara
  • Patent number: 7298039
    Abstract: In order to provide a low-cost and high heat-radiating electronic circuit device featuring high compactness, little warpage, high air tightness, high moldability, high mass productivity, high reliability against thermal shocks, and high oil-proof reliability, a module structure made by packing a whole multi-layer circuit board which connects a semiconductor operating element, semiconductor memory elements, and passive elements thereon and part of a supporting material on which said multi-layer circuit board is placed into a single package by transfer-molding; wherein said multi-layer circuit board and said supporting material are bonded together with a compound metallic material made up from copper oxide and at least one metal selected from a set of gold, silver, and copper.
    Type: Grant
    Filed: August 4, 2004
    Date of Patent: November 20, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Nobutake Tsuyuno, Toshiaki Ishii, Toshiya Satoh, Mitsuhiro Masuda
  • Patent number: 7217992
    Abstract: Semiconductor devices,-semiconductor wafers, and semiconductor modules are provided: wherein the semiconductor device has a small warp; damages at chip edge and cracks in a dropping test are scarcely generated; and the semiconductor device is superior in mounting reliability and mass producibility. The semiconductor device 17 comprising: a semiconductor chip 64; a porous stress relaxing layer 3 provided on the plane, whereon circuits and electrodes are formed, of the semiconductor chip; a circuit layer 2 provided on the stress relaxing layer and connected to the electrodes; and external terminals 10 provided on the circuit layer; wherein an organic protecting film 7 is formed on the plane, opposite to the stress relaxing layer, of the semiconductor chip, and respective side planes of the stress relaxing layer, the semiconductor chip 6, and the protecting film 7 are exposed outside on a same plane.
    Type: Grant
    Filed: June 7, 2004
    Date of Patent: May 15, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Masahiko Ogino, Takumi Ueno, Shuji Eguchi, Akira Nagai, Toshiya Satoh, Toshiaki Ishii, Hiroyoshi Kokaku, Tadanori Segawa, Nobutake Tsuyuno, Asao Nishimura, Ichiro Anjoh
  • Patent number: 7202570
    Abstract: A semiconductor device having a superior connection reliability is obtained by providing a buffer body for absorbing the difference of thermal expansion between the mounting substrate and the semiconductor element in a semiconductor package structure, even if an organic material is used for the mounting substrate. A film material is used as the body for buffering the thermal stress generated by the difference in thermal expansion between the mounting substrate and the semiconductor element. The film material has modulus of elasticity of at least 1 MPa in the reflow temperature range (200–250° C.).
    Type: Grant
    Filed: December 1, 2003
    Date of Patent: April 10, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Akira Nagai, Shuji Eguchi, Masahiko Ogino, Masanori Segawa, Toshiak Ishii, Nobutake Tsuyuno, Hiroyoshi Kokaku, Rie Hattori, Makoto Morishima, Ichiro Anjoh, Kunihiro Tsubosaki, Chuichi Miyazaki, Makoto Kitano, Mamoru Mita, Norio Okabe
  • Patent number: 6888230
    Abstract: Semiconductor devices, semiconductor wafers, and semiconductor modules are provided, wherein: the semiconductor device has a small warp; damage at the chip edge and cracks occurring in a dropping test are scarcely generated; and the semiconductor device is superior in mounting reliability and mass producibility. The semiconductor includes a semiconductor chip 64; a porous stress relaxing layer 3 provided on the plane, whereon circuits and electrodes are formed, of the semiconductor chip; a circuit layer 2 provided on the stress relaxing layer and connected to the electrodes; and external terminals 10 provided on the circuit layer; wherein an organic protecting film 7 is formed on the plane, opposite to the stress relaxing layer, of the semiconductor chip, and respective side planes of the stress relaxing layer, the semiconductor chip 6, and the protecting film 7 are exposed outside on the same plane.
    Type: Grant
    Filed: October 28, 1999
    Date of Patent: May 3, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Masahiko Ogino, Takumi Ueno, Shuji Eguchi, Akira Nagai, Toshiya Satoh, Toshiaki Ishii, Hiroyoshi Kokaku, Tadanori Segawa, Nobutake Tsuyuno, Asao Nishimura, Ichiro Anjoh
  • Publication number: 20050030823
    Abstract: In order to provide a low-cost and high heat-radiating electronic circuit device featuring high compactness, little warpage, high air tightness, high moldability, high mass productivity, high reliability against thermal shocks, and high oil-proof reliability, a module structure made by packing a whole multi-layer circuit board which connects a semiconductor operating element, semiconductor memory elements, and passive elements thereon and part of a supporting material on which said multi-layer circuit board is placed into a single package by transfer-molding; wherein said multi-layer circuit board and said supporting material are bonded together with a compound metallic material made up from copper oxide and at least one metal selected from a set of gold, silver, and copper.
    Type: Application
    Filed: August 4, 2004
    Publication date: February 10, 2005
    Inventors: Nobutake Tsuyuno, Toshiaki Ishii, Toshiya Satoh, Mitsuhiro Masuda
  • Publication number: 20040224149
    Abstract: The object of the present invention is provide a semiconductor device in semiconductor package configuration, characterized by excellent connection reliability ensured by incorporating a buffer for absorbing differences in thermal expansion rate between a mounting substrate and a semiconductor element even when an organic material is used for a mounting substrate.
    Type: Application
    Filed: December 1, 2003
    Publication date: November 11, 2004
    Inventors: Akira Nagai, Shuji Eguchi, Masahiko Ogino, Masanori Segawa, Toshiak Ishii, Nobutake Tsuyuno, Hiroyoshi Kokaku, Rie Hattori, Makoto Morishima, Ichiro Anjoh, Kunihiro Tsubosaki, Chuichi Miyazaki, Makoto Kitano, Mamoru Mita, Norio Okabe
  • Publication number: 20040217453
    Abstract: Semiconductor devices,-semiconductor wafers, and semiconductor modules are provided: wherein the semiconductor device has a small warp; damages at chip edge and cracks in a dropping test are scarcely generated; and the semiconductor device is superior in mounting reliability and mass producibility.
    Type: Application
    Filed: June 7, 2004
    Publication date: November 4, 2004
    Inventors: Masahiko Ogino, Takumi Ueno, Shuji Eguchi, Akira Nagai, Toshiya Satoh, Toshiaki Ishii, Hiroyoshi Kokaku, Tadanori Segawa, Nobutake Tsuyuno, Asao Nishimura, Ichiro Anjoh
  • Publication number: 20040212965
    Abstract: A resin-sealed electronic circuit apparatus capable of maintaining a high heat-dissipating property and packaging density in applications where high hermetic-sealing property and durability are required. The electronic circuit apparatus comprises at least two wiring circuit boards 12 and 13 on which electronic components are mounted. The wiring circuit boards 12 and 13 are fixed to a heat sink 14 having a high heat conductivity via an adhesive 9 and 10. The entirety of the wiring circuit boards 12 and 13 and heat sink 14, as well as a part of an external connection terminal 8 are hermetically sealed and integrally molded by a thermosetting resin composition 7. The electronic circuit apparatus is small and highly reliable and can be provided at low cost.
    Type: Application
    Filed: March 17, 2004
    Publication date: October 28, 2004
    Inventors: Toshiaki Ishii, Nobutake Tsuyuno, Mitsuhiro Masuda, Noriyoshi Urushiwara, Akira Matsushita
  • Patent number: 6791194
    Abstract: A semiconductor device having a superior connection reliability is obtained by providing a buffer body for absorbing the difference of thermal expansion between the mounting substrate and the semiconductor element in a semiconductor package structure, even if an organic material is used for mounting substrate. A film material is used as the body for buffering the thermal stress generated by the difference in thermal expansion between the mounting substrate and the semiconductor element. The film material has modulus of elasticity of at least 1 MPa in the reflow temperature range (200-250° C.).
    Type: Grant
    Filed: January 28, 2000
    Date of Patent: September 14, 2004
    Assignees: Hitachi, Ltd., Hitachi Cable, Ltd.
    Inventors: Akira Nagai, Shuji Eguchi, Masahiko Ogino, Masanori Segawa, Toshiak Ishii, Nobutake Tsuyuno, Hiroyoshi Kokaku, Rie Hattori, Makoto Morishima, Ichiro Anjoh, Kunihiro Tsubosaki, Chuichi Miyazaki, Makoto Kitano, Mamoru Mita, Norio Okabe
  • Publication number: 20020160185
    Abstract: A semiconductor device having a superior connection reliability is obtained by providing a buffer body for absorbing the difference of thermal expansion between the mounting substrate and the semiconductor element in a semiconductor package structure, even if an organic material is used for the mounting substrate. A film material is used as the body for buffering the thermal stress generated by the difference in thermal expansion between the mounting substrate and the semiconductor element. The film material has modulus of elasticity of at least 1 MPa in the reflow temperature range (200-250° C.).
    Type: Application
    Filed: May 6, 2002
    Publication date: October 31, 2002
    Inventors: Akira Nagai, Shuji Eguchi, Masahiko Ogino, Masanori Segawa, Toshiak Ishii, Nobutake Tsuyuno, Hiroyoshi Kokaku, Rie Hattori, Makoto Morishima, Ichiro Anjoh, Kunihiro Tsubosaki, Chuichi Miyazaki, Makoto Kitano, Mamoru Mita, Norio Okabe
  • Patent number: 6114753
    Abstract: A semiconductor device having a superior connection reliability is obtained by providing a buffer body for absorbing the difference of thermal expansion between the mounting substrate and the semiconductor element in a semiconductor package structure, even if an organic material is used for the mounting substrate. A film material is used as the body for buffering the thermal stress generated by the difference in thermal expansion between the mounting substrate and the semiconductor element. The film material has modulus of elasticity of at least 1 MPa in the reflow temperature range (200-250.degree. C.).
    Type: Grant
    Filed: May 16, 1997
    Date of Patent: September 5, 2000
    Assignees: Hitachi, Ltd., Hitachi Cable, Ltd.
    Inventors: Akira Nagai, Shuji Eguchi, Masahiko Ogino, Masanori Segawa, Toshiak Ishii, Nobutake Tsuyuno, Hiroyoshi Kokaku, Rie Hattori, Makoto Morishima, Ichiro Anjoh, Kunihiro Tsubosaki, Chuichi Miyazaki, Makoto Kitano, Mamoru Mita, Norio Okabe
  • Patent number: 6097100
    Abstract: A resin encapsulated semiconductor element is encapsulated with resin composition containing an organic compound selected from the group consisting of organobromine compounds, organophosphorus compounds and organonitrogen compounds, an inorganic filler, and a metal borate. The obtained resin encapsulated semiconductor element has the same flame resistance as a conventional semiconductor element which is encapsulated with a resin composition containing a halogen and antimony compound, and furthermore, has remarkably improved reliabilities regarding moisture resistance and storing at a high temperature by effects of the contained metal borate for suppressing generation of or trapping released gas components, such as halogen or phosphorus, and others.
    Type: Grant
    Filed: August 20, 1997
    Date of Patent: August 1, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Shuji Eguchi, Yasuhide Sugawara, Toshiaki Ishii, Hiroyoshi Kokaku, Akira Nagai, Ryou Moteki, Ogino Masahiko, Masanori Segawa, Rie Hattori, Nobutake Tsuyuno, Takumi Ueno, Atsushi Nakamura, Asao Nishimura