Abstract: A display member includes a frame member formed of heat insulation material; an adhesive layer with removable adhesion formed on one side of the frame member to be attached on a window pane; and a synthetic resin plate arranged on the other side of the frame member. The synthetic resin plate is removably provided on the frame member, thereby to form a housing for a printed material in a space defined by the synthetic resin, the frame member, and the window pane.

Abstract: A method for decoding encoded data includes receiving data encoded by replacing each of a plurality of characters with bit strings. The method also includes recording, on the basis of definition information, at least one of the characters as corresponding to each of the bit lengths, and generating decode information based on the number of characters, wherein the decode information includes bit string information for sorting the bit strings in a bit length order that is a predetermined order associated with bit lengths. The method also includes, in response to receiving a particular bit length, generating character information in which the characters are sorted in the bit length order by inserting a character corresponding to the particular bit length into a position corresponding to the particular bit length in an array in which at least one of the bit lengths.

Abstract: A display member includes a frame member formed of heat insulation material; an adhesive layer with removable adhesion formed on one side of the frame member to be attached on a window pane; and a synthetic resin plate arranged on the other side of the frame member. The synthetic resin plate is removably provided on the frame member, thereby to form a housing for a printed material in a space defined by the synthetic resin, the frame member, and the window pane.

Abstract: A hybrid mechanism whereby hardware acceleration is combined with software such that the compression rate achieved is significantly increased while maintaining the original compression ratio (e.g., using full DHT and not SHT or an approximation). The compression acceleration mechanism is applicable to a hardware accelerator tightly coupled with the general purpose processor. The compression task is divided and parallelized between hardware and software wherein each compression task is split into two acceleration requests: a first request that performs SHT encoding using hardware acceleration and provides post-LZ frequency statistics; and a second request that performs SHT decoding and DHT encoding using the DHT generated in software.

Abstract: An apparatus and method are provided for selecting a specific position from a plurality of positions in a memory to which data elements are cyclically written. A specific data element is stored in the plurality of positions. The apparatus comprises a determination unit for determining whether the plurality of positions include any position in a specific area of the memory to which data elements are written in a current cycle. The apparatus further comprises a selection unit for selecting at least one position in the specific area out of the plurality of positions as the specific position if the determination unit determines that the plurality of positions include any position in the specific area, and for selecting at least one position out of the plurality of positions as the specific position if the determination unit determines that the plurality of positions do not include any position in the specific area.

Abstract: A plurality of stored data sequences that match one or more search data sequences are determined. Each of the stored data sequences of the plurality of stored data sequences comprise a plurality of data elements and the stored data sequences are stored in a content addressable memory array. A longest stored data sequence of the plurality of stored data sequences is determined using a plurality of tracing circuits. An address associated with the longest stored data sequence of the plurality of stored data sequences is determined. A count of data elements of the longest stored data sequence of the plurality of stored data sequences is determined.

Abstract: Data is compressed using content addressable memory without disruption despite error using a plurality of content addressable memories to detect sequentially repeating data elements of the data. Compression information is generated for each sequence of repeating data elements that repeat for at least a compression threshold without any one of the plurality of content addressable memories generating an indication of an error for a matching content addressable memory entry. Individual data elements are output for each of the data elements that do not repeat for the compression threshold. Compression information is generated for each sequence of repeating data elements that repeat for at least the compression threshold and then generating a currently searched data element that matches the repeating data elements when any one of the plurality of content addressable memories generates an indication of an error for a content addressable memory entry that matches the currently searched data element.

Abstract: Data encoded by replacing each of a plurality of characters with bit strings is received. On the basis of definition information, at least one of the characters is recorded as corresponding to each of the bit lengths, and decode information is generated based on the number of characters, wherein the decode information includes bit string information for sorting the bit strings in a bit length order that is a predetermined order associated with bit lengths. In response to receiving a particular bit length, character information in which the characters are sorted in the bit length order is generated by inserting a character corresponding to the particular bit length into a position corresponding to the particular bit length in an array in which at least one of the bit lengths.

Abstract: A technique for register mapping in a virtual system includes preparing a register pool that includes a plurality of registers for mapping. A mapping table is prepared that has a register identifier (ID) and information related to each of a plurality of parameters that express an operational state of the virtual system for each of the registers. At the time a register access request is issued by a hardware thread, the register ID for an access target and information related to each of the plurality of parameters that express the operational state during operation is acquired. One of the registers, for which the acquired register ID and information related to each of the plurality of parameters match the register ID and information for each of the plurality of parameters within the mapping table, is set as a mapped register to be accessed per the register access request.

Abstract: A novel and useful hybrid mechanism whereby hardware acceleration is combined with software such that the compression rate achieved is significantly increased while maintaining the original compression ratio (e.g., using full DHT and not SHT or an approximation). The compression acceleration mechanism is applicable to a hardware accelerator tightly coupled with the general purpose processor. The compression task is divided and parallelized between hardware and software wherein each compression task is split into two acceleration requests: a first request that performs SHT encoding using hardware acceleration and provides post-LZ frequency statistics; and a second request that performs SHT decoding and DHT encoding using the DHT generated in software.

Abstract: An image forming apparatus includes a first sheet discharge unit, a second sheet discharge unit, a switching unit configured to cause a sheet discharge destination to switch between the first sheet discharge unit and the second sheet discharge unit, a memory unit configured to store information about drying time of a print medium, a timer unit configured to determine elapse of the drying time of the printed print medium based on the information stored in the memory unit, and a control unit configured to control the switching unit to set the first sheet discharge unit to be the sheet discharge destination based on a determination of the timer unit that a drying time of a print medium discharged to the first sheet discharge unit has elapsed.

Abstract: A method for decoding encoded data. The method includes receiving data encoded by replacing each of a plurality of characters with bit strings. The method also includes recording, on the basis of definition information, at least one of the characters as corresponding to each of the bit lengths, and generating decode information based on the number of characters, wherein the decode information includes bit string information for sorting the bit strings in a bit length order that is a predetermined order associated with bit lengths. The method also includes, in response to receiving a particular bit length, generating character information in which the characters are sorted in the bit length order by inserting a character corresponding to the particular bit length into a position corresponding to the particular bit length in an array in which at least one of the bit lengths.

Abstract: To provide a method and the like for testing a main memory in a multi processor system, which is capable of reducing a test execution time and accordingly a start-up time as compared with the case where a single processor is used for the test. The present invention provides a method for testing a main memory (MM) in a multi processor system (MPS) including a main processor (MP) and multiple sub processors (SP) each having a DMA transfer mechanism and a local store (LS).

Abstract: Various embodiments are provided to reduce a processing time taken when plural bit lengths each assigned to plural strings are converted into plural codes. In one exemplary embodiment, in response to input of the plurality of bit lengths, a number of strings assigned each of the bit lengths, a bit length assigned to each of the strings, and a sequence number of each string in a group of strings assigned each of the bit lengths are recorded. A plurality of base codes are generated on the basis of the numbers of the strings recorded by the recording unit, the base codes each being a code used as a base for codes having the same one of the bit lengths. A plurality of codes is generated by performing in parallel a plurality of processes respectively for the plurality of strings.

Abstract: An apparatus and method are provided for selecting a specific position from a plurality of positions in a memory to which data elements are cyclically written. A specific data element is stored in the plurality of positions. The apparatus comprises a determination unit for determining whether the plurality of positions include any position in a specific area of the memory to which data elements are written in a current cycle. The apparatus further comprises a selection unit for selecting at least one position in the specific area out of the plurality of positions as the specific position if the determination unit determines that the plurality of positions include any position in the specific area, and for selecting at least one position out of the plurality of positions as the specific position if the determination unit determines that the plurality of positions do not include any position in the specific area.

Abstract: Various embodiments are provided to reduce a processing time taken when plural bit lengths each assigned to plural strings are converted into plural codes. In one exemplary embodiment, in response to input of the plurality of bit lengths, a number of strings assigned each of the bit lengths, a bit length assigned to each of the strings, and a sequence number of each string in a group of strings assigned each of the bit lengths are recorded. A plurality of base codes are generated on the basis of the numbers of the strings recorded by the recording unit, the base codes each being a code used as a base for codes having the same one of the bit lengths. A plurality of codes is generated by performing in parallel a plurality of processes respectively for the plurality of strings.

Abstract: A protector (10) has two half members (20, 40) forming a tubular shape upon being assembled. One half member (20) includes a pair of temporary fixing ribs (26A, 26B) projecting more than a contact edge (23) with the other half member (40) and standing up at the opposite sides of each of corrugated tubes (80A, 80B), each pair of temporary fixing ribs (26A, 26B) are shaped to be insertable into grooves (81A, 81B) of the corresponding corrugated tube (80A, 80B), and stand-up ends (27A, 27B) of the pair of temporary fixing ribs (26A, 26B) are bent to approach each other along the groove (81A, 81B) of the corrugated tube (80A, 80B).

Abstract: To provide a method and the like for testing a main memory in a multi processor system, which is capable of reducing a test execution time and accordingly a start-up time as compared with the case where a single processor is used for the test. The present invention provides a method for testing a main memory (MM) in a multi processor system (MPS) including a main processor (MP) and multiple sub processors (SP) each having a DMA transfer mechanism and a local store (LS).

Abstract: An image defect correction system using directional detection. An image data memory stores a two-dimensional image data output from an image capturing device. A decision means decides whether a target pix cell is a defective pix cell by deciding whether an image data of the target pix cell is a prominent spot using a plurality of image data of the target pix cell and 8 adjacent pix cells arranged in 4 directions of upper-lower, left-right, lower-right and upper-right, counting direction number having the prominent spot, and deciding whether the target pix cell is the defective pix cell according to the counted direction number. A replacement means replaces the image data of the target pix cell with a predetermined image data when the target pix cell is determined to be the defective pix cell.

Abstract: A floor cushion with a seat back has excellent ease of storage and is designed to improve heat preservation by adjusting the cushion size to a chair or increasing its fitting property. The floor cushion includes a sheet-like seat portion, a sheet-like seat back portion foldably connected to a rear part of the seat portion, and sheet-like sleeve portions foldably connected to both sides of the seat portion. The sheet-like portion extends at a required length beyond the rear part of the seat portion, and extensions of the respective sleeve portions are attached to the back face of the seat back portion, thereby enabling fixing of the respective extensions and the seat back portion to each other, detachably and in a way to allow positional adjustment with hook-and-loop fasteners.