Patents by Inventor Noriaki Maeda
Noriaki Maeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8483003Abstract: Disclosed is a semiconductor device in which substantial enhancement of a write margin without degradation of a static noise can be achieved while obviating an increase in physical circuit size. There are disposed a plurality of power supply lines for feeding a power supply voltage to each column of static memory cells that use complementary bit lines in common; a plurality of power switches, each being disposed for each of the power supply lines; and a plurality of short-circuit switches, each being so arranged as to provide short-circuiting between output nodes of different power switches.Type: GrantFiled: March 1, 2011Date of Patent: July 9, 2013Assignee: Renesas Electronics CorporationInventor: Noriaki Maeda
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Patent number: 8441843Abstract: The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.Type: GrantFiled: October 31, 2011Date of Patent: May 14, 2013Assignee: Renesas Electronics CorporationInventors: Noriaki Maeda, Yoshihiro Shinozaki, Masanao Yamaoka, Yasuhisa Shimazaki, Masanori Isoda, Koji Nii
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Publication number: 20130026580Abstract: A semiconductor device having an SRAM which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a second active region separated from the first active region, in which a second transistor is disposed; a monolithic third active region in which a third transistor and a sixth transistor are disposed; and a fourth active region separated from the third active region, in which a fourth transistor is disposed. Each driver transistor is divided into a first transistor and a second transistor (or a third transistor and a fourth transistor) and these driver transistors are disposed over different active regions.Type: ApplicationFiled: July 26, 2012Publication date: January 31, 2013Inventors: Masao Morimoto, Noriaki Maeda, Yasuhisa Shimazaki
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Publication number: 20120326240Abstract: A semiconductor device includes a first MISFET and a second MISFET which are formed over a semiconductor substrate and have the same conductive type. The first MISFET has a first gate insulating film arranged over the semiconductor substrate, a first gate electrode arranged over the first gate insulating film, and a first source region and a first drain region. The second MISFET has a second gate insulating film arranged over the semiconductor substrate, a second gate electrode arranged over the second gate insulating film, and a second source region and a second drain region. The first and the second gate electrode are electrically coupled, the first and the second source region are electrically coupled, and the first and the second drain region are electrically coupled. Accordingly, the first and the second MISFET are coupled in parallel. In addition, threshold voltages are different between the first and the second MISFET.Type: ApplicationFiled: September 7, 2012Publication date: December 27, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Noriaki Maeda
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Patent number: 8319292Abstract: A semiconductor device includes a first MISFET and a second MISFET which are formed over a semiconductor substrate and have the same conductive type. The first MISFET has a first gate insulating film arranged over the semiconductor substrate, a first gate electrode arranged over the first gate insulating film, and a first source region and a first drain region. The second MISFET has a second gate insulating film arranged over the semiconductor substrate, a second gate electrode arranged over the second gate insulating film, and a second source region and a second drain region. The first and the second gate electrode are electrically coupled, the first and the second source region are electrically coupled, and the first and the second drain region are electrically coupled. Accordingly, the first and the second MISFET are coupled in parallel. In addition, threshold voltages are different between the first and the second MISFET.Type: GrantFiled: June 27, 2011Date of Patent: November 27, 2012Assignee: Renesas Electronics CorporationInventor: Noriaki Maeda
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Patent number: 8125845Abstract: Even when memory capacity of a memory that uses a replica bit-line is made higher, fluctuations of a generating timing of a sense-amplifier enable signal are reduced. A semiconductor integrated circuit device comprises a plurality of word lines, a plurality of bit-lines, a plurality of ordinary memory cells, an access control circuit, a plurality of sense-amplifiers, first and second replica bit-lines, first and second replica memory cells, and first and second logic circuits. The first and second replica memory cells are connected to the first and second replica bit-lines, respectively; inputs of the first and second logic circuits are connected to the first and second replica bit-lines, respectively; a sense-amplifier enable signal is generated from an output of the second logic circuit; and this signal is supplied to a plurality of sense-amplifiers.Type: GrantFiled: January 14, 2010Date of Patent: February 28, 2012Assignee: Renesas Electronics CorporationInventors: Shigenobu Komatsu, Masanao Yamaoka, Noriaki Maeda, Masao Morimoto, Yasuhisa Shimazaki
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Publication number: 20120044775Abstract: The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.Type: ApplicationFiled: October 31, 2011Publication date: February 23, 2012Inventors: Noriaki Maeda, Yoshihiro Shinozaki, Masanao Yamaoka, Yasuhisa Shimazaki, Masanori Isoda, Koji Nii
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Patent number: 8072799Abstract: The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.Type: GrantFiled: March 29, 2010Date of Patent: December 6, 2011Assignee: Renesas Electronics CorporationInventors: Noriaki Maeda, Yoshihiro Shinozaki, Masanao Yamaoka, Yasuhisa Shimazaki, Masanori Isoda, Koji Nii
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Publication number: 20110254104Abstract: A semiconductor device includes a first MISFET and a second MISFET which are formed over a semiconductor substrate and have the same conductive type. The first MISFET has a first gate insulating film arranged over the semiconductor substrate, a first gate electrode arranged over the first gate insulating film, and a first source region and a first drain region. The second MISFET has a second gate insulating film arranged over the semiconductor substrate, a second gate electrode arranged over the second gate insulating film, and a second source region and a second drain region. The first and the second gate electrode are electrically coupled, the first and the second source region are electrically coupled, and the first and the second drain region are electrically coupled. Accordingly, the first and the second MISFET are coupled in parallel. In addition, threshold voltages are different between the first and the second MISFET.Type: ApplicationFiled: June 27, 2011Publication date: October 20, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventor: Noriaki Maeda
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Publication number: 20110216610Abstract: Disclosed is a semiconductor device in which substantial enhancement of a write margin without degradation of a static noise can be achieved while obviating an increase in physical circuit size. There are disposed a plurality of power supply lines for feeding a power supply voltage to each column of static memory cells that use complementary bit lines in common; a plurality of power switches, each being disposed for each of the power supply lines; and a plurality of short-circuit switches, each being so arranged as to provide short-circuiting between output nodes of different power switches.Type: ApplicationFiled: March 1, 2011Publication date: September 8, 2011Inventor: Noriaki MAEDA
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Patent number: 7989897Abstract: A semiconductor device includes a first MISFET and a second MISFET which are formed over a semiconductor substrate and have the same conductive type. The first MISFET has a first gate insulating film arranged over the semiconductor substrate, a first gate electrode arranged over the first gate insulating film, and a first source region and a first drain region. The second MISFET has a second gate insulating film arranged over the semiconductor substrate, a second gate electrode arranged over the second gate insulating film, and a second source region and a second drain region. The first and the second gate electrode are electrically coupled, the first and the second source region are electrically coupled, and the first and the second drain region are electrically coupled. Accordingly, the first and the second MISFET are coupled in parallel. In addition, threshold voltages are different between the first and the second MISFET.Type: GrantFiled: November 26, 2008Date of Patent: August 2, 2011Assignee: Renesas Electronics CorporationInventor: Noriaki Maeda
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Publication number: 20110063895Abstract: A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.Type: ApplicationFiled: August 12, 2010Publication date: March 17, 2011Inventors: Shigenobu KOMATSU, Masanao Yamaoka, Noriaki Maeda, Masao Morimoto, Yasuhisa Shimazaki, Yasuyuki Okuma, Toshiaki Sano
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Publication number: 20110003757Abstract: The present invention provides a pharmaceutical composition useful as a therapeutic agent for fatty liver disease. A pharmaceutical composition, which comprises (1S)-1,5-anhydro-1-[5-(azulen-2-ylmethyl)-2-hydroxyphenyl]-D-glucitol or a pharmaceutically acceptable salt thereof, (1S)-1,5-anhydro-1-[3-(1-benzothiophen-2-ylmethyl)-4-fluorophenyl]-D-glucitol or a pharmaceutically acceptable salt thereof, or alternatively, (1S)-1,5-anhydro-1-[4-chloro-3-(4-ethoxybenzyl)phenyl]-D-glucitol or a pharmaceutically acceptable salt thereof, more specifically such a pharmaceutical composition for treating fatty liver disease, such as nonalcoholic fatty liver disease in one embodiment, or nonalcoholic simple fatty liver and/or nonalcoholic steatohepatitis in another embodiment.Type: ApplicationFiled: January 29, 2009Publication date: January 6, 2011Applicants: ASTELLAS PHARMA INC., KOTOBUKI PHARMACEUTICAL CO., LTD.Inventors: Eiji Kurosaki, Toshiyuki Takasu, Noriaki Maeda, Shunji Yamazaki
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Publication number: 20100188887Abstract: The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.Type: ApplicationFiled: March 29, 2010Publication date: July 29, 2010Inventors: Noriaki Maeda, Yoshihiro Shinozaki, Masanao Yamaoka, Yasuhisa Shimazaki, Masanori Isoda, Koji Nii
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Publication number: 20100177580Abstract: Even when memory capacity of a memory that uses a replica bit-line is made higher, fluctuations of a generating timing of a sense-amplifier enable signal are reduced. A semiconductor integrated circuit device comprises a plurality of word lines, a plurality of bit-lines, a plurality of ordinary memory cells, an access control circuit, a plurality of sense-amplifiers, first and second replica bit-lines, first and second replica memory cells, and first and second logic circuits. The first and second replica memory cells are connected to the first and second replica bit-lines, respectively; inputs of the first and second logic circuits are connected to the first and second replica bit-lines, respectively; a sense-amplifier enable signal is generated from an output of the second logic circuit; and this signal is supplied to a plurality of sense-amplifiers.Type: ApplicationFiled: January 14, 2010Publication date: July 15, 2010Inventors: Shigenobu Komatsu, Masanao Yamaoka, Noriaki Maeda, Masao Morimoto, Yasuhisa Shimazaki
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Patent number: 7715223Abstract: The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.Type: GrantFiled: December 5, 2008Date of Patent: May 11, 2010Assignee: Renesas Technology Corp.Inventors: Noriaki Maeda, Yoshihiro Shinozaki, Masanao Yamaoka, Yasuhisa Shimazaki, Masanori Isoda, Koji Nll
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Patent number: 7640966Abstract: An object of the invention is to provide a heat exchanger (radiator) or a cooling module having the radiator and a condenser, which has a higher rigidity against vibration in the vertical direction. To the end, the radiator or the cooling module is mounted to a vehicle by mounting brackets, which are fixed to the radiator tanks at their vertical ends. The mounting brackets have mounting pins, with which the radiator or the cooling module is mounted to the vehicle.Type: GrantFiled: December 6, 2004Date of Patent: January 5, 2010Assignee: DENSO CorporationInventors: Akihiro Maeda, Yoshihiko Kamiya, Harumi Okai, Noriaki Maeda, Masami Tamura
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Publication number: 20090194823Abstract: A semiconductor device includes a first MISFET and a second MISFET which are formed over a semiconductor substrate and have the same conductive type. The first MISFET has a first gate insulating film arranged over the semiconductor substrate, a first gate electrode arranged over the first gate insulating film, and a first source region and a first drain region. The second MISFET has a second gate insulating film arranged over the semiconductor substrate, a second gate electrode arranged over the second gate insulating film, and a second source region and a second drain region. The first and the second gate electrode are electrically coupled, the first and the second source region are electrically coupled, and the first and the second drain region are electrically coupled. Accordingly, the first and the second MISFET are coupled in parallel. In addition, threshold voltages are different between the first and the second MISFET.Type: ApplicationFiled: November 26, 2008Publication date: August 6, 2009Inventor: Noriaki MAEDA
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Publication number: 20090116279Abstract: The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.Type: ApplicationFiled: December 5, 2008Publication date: May 7, 2009Inventors: Noriaki Maeda, Yoshihiro Shinozaki, Masanao Yamaoka, Yasuhisa Shimazaki, Masanori Isoda, Koji Nll
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Patent number: 7477537Abstract: The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.Type: GrantFiled: August 15, 2006Date of Patent: January 13, 2009Assignee: Renesas Technology Corp.Inventors: Noriaki Maeda, Yoshihiro Shinozaki, Masanao Yamaoka, Yasuhisa Shimazaki, Masanori Isoda, Koji Nii