Patents by Inventor Noriaki Maeda

Noriaki Maeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080247258
    Abstract: A leakage current of the MOS transistor of a power control section at a standby time is drastically reduced and the reduction of the consumption power is achieved. A memory module is provided with power control sections. When either of the memory mats is not selected, the power control sections stop the power supply voltage to a non-selected memory mat, a word driver, an input-output circuit, a control circuit and an output circuit. At the standby time of the memory module, the power control section stops a power supply to power control sections, a control circuit, a predecoder circuit, and an input circuit. In this manner, the leakage current of the MOS transistor of the power control sections at the standby time can be drastically reduced.
    Type: Application
    Filed: May 9, 2008
    Publication date: October 9, 2008
    Inventors: Noriyoshi WATANABE, Noriaki Maeda, Masanao Yamaoka, Yoshihiro Shinozaki
  • Patent number: 7420834
    Abstract: The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.
    Type: Grant
    Filed: August 15, 2006
    Date of Patent: September 2, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Noriaki Maeda, Yoshihiro Shinozaki, Masanao Yamaoka, Yasuhisa Shimazaki, Masanori Isoda, Koji Nii
  • Patent number: 7385870
    Abstract: A leakage current of the MOS transistor of a power control section at a standby time is drastically reduced and the reduction of the consumption power is achieved. A memory module is provided with power control sections. When either of the memory mats is not selected, the power control sections stop the power supply voltage to a non-selected memory mat, a word driver, an input-output circuit, a control circuit and an output circuit. At the standby time of the memory module, the power control section stops a power supply to power control sections, a control circuit, a predecoder circuit, and an input circuit. In this manner, the leakage current of the MOS transistor of the power control sections at the standby time can be drastically reduced.
    Type: Grant
    Filed: June 20, 2007
    Date of Patent: June 10, 2008
    Assignees: Renesas Technology Corp., SuperH, Inc., Renesas Northern Japan Semiconductor, Inc., Hitachi ULSI Systems Co., Ltd.
    Inventors: Noriyoshi Watanabe, Noriaki Maeda, Masanao Yamaoka, Yoshihiro Shinozaki
  • Publication number: 20070247952
    Abstract: A leakage current of the MOS transistor of a power control section at a standby time is drastically reduced and the reduction of the consumption power is achieved. A memory module is provided with power control sections. When either of the memory mats is not selected, the power control sections stop the power supply voltage to a non-selected memory mat, a word driver, an input-output circuit, a control circuit and an output circuit. At the standby time of the memory module, the power control section stops a power supply to power control sections, a control circuit, a predecoder circuit, and an input circuit. In this manner, the leakage current of the MOS transistor of the power control sections at the standby time can be drastically reduced.
    Type: Application
    Filed: June 20, 2007
    Publication date: October 25, 2007
    Inventors: Noriyoshi Watanabe, Noriaki Maeda, Masanao Yamaoka, Yoshihiro Shinozaki
  • Patent number: 7251182
    Abstract: A leakage current of the MOS transistor of a power control section at a standby time is drastically reduced and the reduction of the consumption power is achieved. A memory module is provided with power control sections. When either of the memory mats is not selected, the power control sections stop the power supply voltage to a non-selected memory mat, a word driver, an input-output circuit, a control circuit and an output circuit. At the standby time of the memory module, the power control section stops a power supply to power control sections, a control circuit, a predecoder circuit, and an input circuit. In this manner, the leakage current of the MOS transistor of the power control sections at the standby time can be drastically reduced.
    Type: Grant
    Filed: February 15, 2006
    Date of Patent: July 31, 2007
    Assignees: Renesas Technology Corp., SuperH, Inc., Renesas Northern Japan Semiconductor, Inc., Hitachi ULSI Systems Co., Ltd.
    Inventors: Noriyoshi Watanabe, Noriaki Maeda, Masanao Yamaoka, Yoshihiro Shinozaki
  • Publication number: 20060274572
    Abstract: The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.
    Type: Application
    Filed: August 15, 2006
    Publication date: December 7, 2006
    Inventors: Noriaki Maeda, Yoshihiro Shinozaki, Masanao Yamaoka, Yasuhisa Shimazaki, Masanori Isoda, Koji Nii
  • Publication number: 20060274571
    Abstract: The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.
    Type: Application
    Filed: August 15, 2006
    Publication date: December 7, 2006
    Inventors: Noriaki Maeda, Yoshihiro Shinozaki, Masanao Yamaoka, Yasuhisa Shimazaki, Masanori Isoda, Koji Nii
  • Patent number: 7113421
    Abstract: The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.
    Type: Grant
    Filed: May 12, 2005
    Date of Patent: September 26, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Noriaki Maeda, Yoshihiro Shinozaki, Masanao Yamaoka, Yasuhisa Shimazaki, Masanori Isoda, Koji Nii
  • Publication number: 20060133180
    Abstract: A leakage current of the MOS transistor of a power control section at a standby time is drastically reduced and the reduction of the consumption power is achieved. A memory module is provided with power control sections. When either of the memory mats is not selected, the power control sections stop the power supply voltage to a non-selected memory mat, a word driver, an input-output circuit, a control circuit and an output circuit. At the standby time of the memory module, the power control section stops a power supply to power control sections, a control circuit, a predecoder circuit, and an input circuit. In this manner, the leakage current of the MOS transistor of the power control sections at the standby time can be drastically reduced.
    Type: Application
    Filed: February 15, 2006
    Publication date: June 22, 2006
    Inventors: Noriyoshi Watanabe, Noriaki Maeda, Masanao Yamaoka, Yoshihiro Shinozaki
  • Patent number: 7031220
    Abstract: A leakage current of the MOS transistor of a power control section at a standby time is drastically reduced and the reduction of the consumption power is achieved. A memory module is provided with power control sections. When either of the memory mats is not selected, the power control sections stop the power supply voltage to a non-selected memory mat, a word driver, an input-output circuit, a control circuit and an output circuit. At the standby time of the memory module, the power control section stops a power supply to power control sections, a control circuit, a predecoder circuit, and an input circuit. In this manner, the leakage current of the MOS transistor of the power control sections at the standby time can be drastically reduced.
    Type: Grant
    Filed: August 27, 2004
    Date of Patent: April 18, 2006
    Assignees: Renesas Technology Corp, SuperH, Inc., Renesas Northern Japan Semiconductor, Inc., Hitachi ULSI Systems Co., Ltd.
    Inventors: Noriyoshi Watanabe, Noriaki Maeda, Masanao Yamaoka, Yoshihiro Shinozaki
  • Patent number: 7021411
    Abstract: A clearance 44 is provided between the outer periphery of a duct 42 and a vehicle body, that is, a radiator support 50 and, at the same time, the clearance 44 is made to have a labyrinth structure. In this structure, it is possible to prevent vibrations of the vehicle body from being propagated from the radiator support 50 to the duct 42 while preventing a current of air, such as one caused by movement of the vehicle, from flowing around heat exchangers, such as a radiator 10, and flowing downstream through the clearance 44. Therefore, it is possible to improve the cooling performance of heat exchangers such as the radiator 10 while preventing the duct 42, that is, a duct shroud 40 from being damaged by vibration.
    Type: Grant
    Filed: March 3, 2003
    Date of Patent: April 4, 2006
    Assignee: DENSO Corporation
    Inventors: Noriaki Maeda, Ikuo Ozawa, Toshiki Sugiyama
  • Publication number: 20060056229
    Abstract: The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.
    Type: Application
    Filed: May 12, 2005
    Publication date: March 16, 2006
    Inventors: Noriaki Maeda, Yoshihiro Shinozaki, Masanao Yamaoka, Yasuhisa Shimazaki, Masanori Isoda, Koji Nii
  • Publication number: 20050121170
    Abstract: An object of the invention is to provide a heat exchanger (radiator) or a cooling module having the radiator and a condenser, which has a higher rigidity against vibration in the vertical direction. To the end, the radiator or the cooling module is mounted to a vehicle by mounting brackets, which are fixed to the radiator tanks at their vertical ends. The mounting brackets have mounting pins, with which the radiator or the cooling module is mounted to the vehicle.
    Type: Application
    Filed: December 6, 2004
    Publication date: June 9, 2005
    Inventors: Akihiro Maeda, Yoshihiko Kamiya, Harumi Okai, Noriaki Maeda, Masami Tamura
  • Patent number: 6883589
    Abstract: A front end structure includes a front end panel (400) that is configured as a duct structure for preventing the air introduced from a grille opening (452) from bypassing a condenser (200) and a radiator (100). A fan unit (300) is arranged on the most upstream side portion of the structure. As a result, without the need to provide parts making up a separate duct structure, fresh air flow temperature can be blown in, while at the same time, the air that has passed through the condenser (200) can be prevented from bypassing the radiator (100). Thus, the heat releasing capacity of the condenser (200) and the radiator (100) can be improved while simultaneously preventing leakage between the condenser (200) and the radiator (100) without adding complex structure.
    Type: Grant
    Filed: September 26, 2001
    Date of Patent: April 26, 2005
    Assignee: Denso Corporation
    Inventors: Ikuo Ozawa, Toshiki Sugiyama, Norihisa Sasano, Noriaki Maeda, Shun Kurata
  • Publication number: 20050052925
    Abstract: A leakage current of the MOS transistor of a power control section at a standby time is drastically reduced and the reduction of the consumption power is achieved. A memory module is provided with power control sections. When either of the memory mats is not selected, the power control sections stop the power supply voltage to a non-selected memory mat, a word driver, an input-output circuit, a control circuit and an output circuit. At the standby time of the memory module, the power control section stops a power supply to power control sections, a control circuit, a predecoder circuit, and an input circuit. In this manner, the leakage current of the MOS transistor of the power control sections at the standby time can be drastically reduced.
    Type: Application
    Filed: August 27, 2004
    Publication date: March 10, 2005
    Inventors: Noriyoshi Watanabe, Noriaki Maeda, Masanao Yamaoka, Yoshihiro Shinozaki
  • Publication number: 20040116530
    Abstract: The invention provides a pharmaceutical composition containing, as the active ingredient thereof, a prostaglandin-I2 agonist, therefore providing a remedy or preventive for various disorders resulting from tissue fibrogenesis.
    Type: Application
    Filed: October 16, 2003
    Publication date: June 17, 2004
    Inventors: Noriaki Maeda, Yasunori Nagakura, Mariko Ota, Yoshitaka Hirayama, Tatsuya Sasakawa, Tomoya Oe
  • Patent number: 6708790
    Abstract: A front-end structure comprising a panel body (400) to which a center member (500), being fixed to a body of a vehicle at a front end of the vehicle and supporting, at least, a driving engine (E/G), is joined, wherein the panel body (400) is molded out of aluminum by die-casting and a joining section (421) of the panel body (400) to which the center member (500) is joined has a mechanical strength higher than that of any other sections of the panel body (400) near the joining section (421) except the joining section (421).
    Type: Grant
    Filed: April 25, 2002
    Date of Patent: March 23, 2004
    Assignee: Denso Corporation
    Inventors: Ikuo Ozawa, Toshiki Sugiyama, Norihisa Sasano, Noriaki Maeda, Kazuaki Kafuku, Harumi Okai, Yasuhiko Itou, Tomoyuki Hatano, Hiromi Takagi, Takeshi Nagasaka, Yasushi Hibi
  • Patent number: 6676283
    Abstract: A vent line (440) for establishing communication between the interior of headlamps (500) and at least a blower (300) is formed integrally with a front end panel (400). The vent line (440) makes up a duct member (441) leading from each of the headlamps (500) to the blower (300). A light controller (560) is assembled by being fixed on the panel (400) in such a manner as to be located at the air inlet (442) of the duct member (441) (vent line (440)).
    Type: Grant
    Filed: June 14, 2001
    Date of Patent: January 13, 2004
    Assignee: Denso Corporation
    Inventors: Ikuo Ozawa, Noriaki Maeda, Harumi Okai, Norihisa Sasano, Toshiki Sugiyama, Hiroaki Okuchi, Yasuhiro Itoh, Kazuaki Kafuku
  • Patent number: 6660969
    Abstract: When a load given to the engine 100 is less than a predetermined value, the outside air suction port 104 is closed and only inside air is supplied to the engine 100, and the valve 112a is opened so as to supply warm water to the heater 112. When the load given to the engine 100 is not less than the predetermined value and the temperature of air outside the engine compartment 11 is lower than a predetermined value, the inside air suction port 102 is closed and only outside air is supplied to the engine 100, and the valve 112a is closed so that the supply of warm water to the heater 112 is stopped.
    Type: Grant
    Filed: July 24, 2002
    Date of Patent: December 9, 2003
    Assignee: Denso Corporation
    Inventors: Ikuo Ozawa, Kazuaki Kafuku, Harumi Okai, Noriaki Maeda, Toshiki Sugiyama, Norihisa Sasano
  • Patent number: 6626483
    Abstract: When the suction opening portion 121 is covered with the decoration grill 300 from the front side of a vehicle, the suction chamber 140 filled with air is formed on the front side of the suction opening portion 121, and the communication passage 141 to connect the suction chamber 140 with the outside of the suction chamber 140 in a direction perpendicular to the longitudinal direction of the vehicle is formed into a labyrinth structure by the decoration grill 300, bumper cover 410 and front end panel 100. Due to the above structure, it is possible to supply air, which has been sucked from the outside of the engine compartment, to the engine while foreign material, such as rain water and snow, is prevented from being sucked into the engine.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: September 30, 2003
    Assignee: Denso Corporation
    Inventors: Ikuo Ozawa, Noriaki Maeda, Norihisa Sasano, Toshiki Sugiyama