Abstract: An exposure mask includes an optically transparent substrate, a device area constituted with a pattern formed on the substrate, and alignment marks formed on the substrate. Further measurement data for relative positional displacement between the device area and the alignment marks on the substrate is appended together with information for identifying the substrate to the substrate.

Abstract: Productivity of a semiconductor integrated circuit device is improved. According to how many times the photomask is used, a photomask having an opaque pattern made of metal and a photomask having an opaque pattern made of a resist film are properly used, and thereby an exposure treatment is performed.

Abstract: The present invention provides a method of manufacturing halftone phase shift masks in less steps to save time and cost and to increase the yield, and a halftone phase shift mask with higher phase—and size controllability. To achieve this, the halftone phase shift mask includes a structure having a shade band of resist film formed on the halftone film delineating fine patterns and around the area of fine pattern.

Abstract: A field oxide film 3 in a region where relief cells are formed is made wider than the field oxide film 3 in a region where normal memory cells are formed thereby to make a field relaxation layer 8r of the relief cells deeper than the field relaxation layer 8 of the normal cells, and the depletion layer of the sources and drains (n-type semiconductor regions) of the relief cells is widened to weaken the junction field.

Abstract: An organic electrically conductive compound represented by general formula (1): 1

Abstract: An organic electrically conductive compound represented by general formula (1): 1

Abstract: The present invention provides a method of manufacturing halftone phase shift masks in less steps to save time and cost and to increase the yield, and a halftone phase shift mask with higher phase- and size controllability. To achieve this, the halftone phase shift mask includes a structure having a shade band of resist film formed on the halftone film delineating fine patterns and around the area of fine pattern.

Abstract: A fabrication method of a semiconductor integrated circuit device, comprises preparing a mask having, on a first main surface of a mask substrate, a first light transmitting region, a second light transmitting region disposed at the periphery of the first light transmitting region and permitting inversion of the phase of a light transmitted through the second light transmitting region relative to a light transmitted through the first light transmitting region, and a light shielding region disposed at the periphery of the second light transmitting region; and transferring a predetermined pattern to a photoresist film over the main surface of a wafer through said mask by a projection exposure reduction treatment, wherein said second light transmitting region is formed from a first film deposited over the first main surface of the mask substrate, said light shielding region is formed by a second film deposited over the first main surface of the mask substrate via said first film, and at least one of said first f

Abstract: In order to inhibit or prevent a pattern abnormality such as the deformation or misalignment of a pattern of a semiconductor integrated circuit device, a light intensity is calculated based on the pattern data DBP of a mask and the aberration data DBL of a lens of a pattern exposure device (step 101) and then the results of the light intensity calculation is compared with the results of the light intensity calculated on condition that the lens of the pattern exposure device has no aberration (step 102), and then a pattern data exceeding an allowable level, of the pattern data of the mask, is corrected according to the amount of correction calculated on the basis of the results of the comparison such that the pattern data does not exceed the allowable level (step 104). The mask is manufactured by using the mask making data DBM after the correction and then is mounted on the pattern exposure device to transfer a predetermined pattern to a semiconductor wafer.

Abstract: A magneto-resistive thin film magnetic head is provided, which magnetic head includes: a base; a first yoke provided on the base and separated by a gap into first and second portions, the first portion including a side which opposes a magnetic recording medium; a magneto-resistive element which is magnetically coupled to the first and second portions of the first yoke and detects a magnetic recording signal; a second yoke formed on the first yoke so as to form a reproducing head gap between the first portion of the first yoke and the second yoke; and a third yoke provided between the first portion of the first yoke and the base so as to be magnetically coupled to the first portion of the first yoke. The reproducing head gap, the first portion of the first yoke, the magneto-resistive element, the second portion of the first yoke, ad the second yoke form a cut magnetic circuit.

Abstract: A pattern accuracy of a semiconductor integrated circuit device is to be improved. When an ordinary photomask is to be replaced with a resist mask, in setting a planar size of a shielding pattern formed by resist film, a correction quantity L is subtracted from a planar size of a corresponding shielding pattern formed of metal. Conversely, when the resist mask is to be replaced with the ordinary mask, in setting a planar size of the shielding pattern formed of metal, the correction quantity L is added to the planar size of the corresponding shielding pattern formed by resist film.

Abstract: A pattern is transferred to a resist film on a wafer by a reduction projection exposure method using a half-tone phase-shift mask in which is formed a half-tone phase-shifter pattern including a thin-film pattern functioning as an attenuator and a resist pattern functioning as the photosensitive composition for phase adjustment. This method improves the accuracy of dimensions of the pattern transferred to the wafer.

Abstract: An active region (L) with a metal insulator semiconductor field effect transistor (MISFET) (Qs) formed therein for selection of a DRAM memory cell, which makes up a memory cell of the DRAM, is arranged to have an island-like pattern that linearly extends in an X direction on one principal surface of a semiconductor substrate (1). The memory-cell selection MISFET (Qs) has an insulated gate electrode (7) (word line WL) that extends along a Y direction on the principal surface of the semiconductor substrate (1) with the same width kept along the length thereof, which gate electrode is arranged to oppose another gate electrode (7) (word line WL) adjacent thereto at a prespecified distance or pitch that is narrower than said width.

Abstract: An active region (L) with a metal insulator semiconductor field effect transistor (MISFET) (Qs) formed therein for selection of a DRAM memory cell, which makes up a memory cell of the DRAM, is arranged to have an island-like pattern that linearly extends in an X direction on one principal surface of a semiconductor substrate (1). The memory-cell selection MISFET (Qs) has an insulated gate electrode (7) (word line WL) that extends along a Y direction on the principal surface of the semiconductor substrate (1) with the same width kept along the length thereof, which gate electrode is arranged to oppose another gate electrode (7) (word line WL) adjacent thereto at a prespecified distance or pitch that is narrower than said width.

Abstract: When a through hole 17 is transferred on a pair of contact holes 10 putting a data line DL therebetween, even if a pair of through holes 17 putting the data line DL therebetween are deviated, the pair of through holes are connected to the contact hole 10b and not connected to the data line DL. By this manner, a mask pattern formed by a photomask is use so as to be deviated and disposed in a direction separately from the data line DL at a design stage. This results in improvement of an alignment tolerance of the pattern.

Abstract: Disclosed is a technique capable of reducing the manufacturing time of a photomask. In a method of transferring a predetermined pattern onto a semiconductor wafer by reduced projection exposure using a product mask manufactured by performing the reduced projection exposure to a pattern of an IP mask Mm1, the IP mask Mm1 is designed to have a resist mask structure in which a light-shielding pattern thereof is constituted of an organic film such as a resist film.

Abstract: A semitransparent phase shifting mask has, in the periphery of a pattern element area, a light shielding portion which is formed by a semitransparent phase shifting portion and a transparent portion with the optimal size combination. A pattern is formed employing the semitransparent phase shifting mask.

Abstract: An area for fabricating a photomask having light-shielding patterns each formed of an organic film, and areas for fabricating a semiconductor integrated circuit device are provided within the same clean room. A manufacturing device and an inspecting device are commonly used upon the fabrication of the photomask and the fabrication of the semiconductor integrated circuit device.

Abstract: A relative positional error is caused between an alignment mark and a device area on a mask due to an error inherent to the mask drawing apparatus, which causes an alignment error in the device area even when alignment upon exposure has no problem. Then, according to this invention, a relative positional error between the alignment mark and the device area on the mask is measured in an off line manner, the result of measurement is set upon exposure as a correction value to an exposure device thereby correcting the mask drawing error to reduce alignment errors in the device area.

Abstract: In the case of a resist mask using a resist as an opaque material, problems occur that a foreign matter is produced due to contact with other equipment and becomes a defect for pattern transfer and the yield of manufactured devices is deteriorated. A device is manufactured by using a photomask provided with a resist pattern to which a resist is not attached for a mechanical contact point with other equipment.