Abstract: A trench is formed in the surface of a provided semiconductor body. An oxide is deposited in the trench and a cap is deposited on the oxide, wherein the combination of the cap and the oxide impart a mechanical stress on the semiconductor body.

Abstract: Disclosed herein is a method for evaluating scratch resistance of a plastic resin comprising scratching a surface of a test sample of plastic resin using a scratch apparatus to form a scratch of the surface having a scratch profile; scanning the scratched test sample with a surface profile analysis apparatus to measure the scratch profile; and creating a scratch resistance evaluation index based on the measured scratch profile to evaluate the scratch resistance of the test sample. The method has good reliability and reproducibility, reduces measurement time and errors caused by measurers and measuring conditions, provides easy measurement and can be widely applied to all plastic resins.

Abstract: A trench is formed in the surface of a provided semiconductor body. An oxide is deposited in the trench and a cap is deposited on the oxide, wherein the combination of the cap and the oxide impart a mechanical stress on the semiconductor body.

Abstract: Methods of forming integrated circuit devices according to embodiments of the present invention include forming a PMOS transistor having P-type source and drain regions, in a semiconductor substrate, and then forming a diffusion barrier layer on the source and drain regions. A silicon nitride layer is deposited on at least portions of the diffusion barrier layer that extend opposite the source and drain regions. Hydrogen is removed from the deposited silicon nitride layer by exposing the silicon nitride layer to ultraviolet (UV) radiation. This removal of hydrogen may operate to increase a tensile stress in a channel region of the field effect transistor. This UV radiation step may be followed by patterning the first and second silicon nitride layers to expose the source and drain regions and then forming silicide contact layers directly on the exposed source and drain regions.

Abstract: Integrated circuit transistors may be fabricated by simultaneously removing a photoresist layer on a first active area of an integrated circuit substrate and a carbon-containing layer on a second active area of the integrated circuit substrate, to expose a nitride stress-generating layer on the second active area. A single mask may be used to define the second active area for removal of the photoresist layer on the first active area and for implanting source/drain regions into the second active area.

Abstract: Methods of forming integrated circuit devices include depositing an electrically insulating layer onto an integrated circuit substrate having integrated circuit structures thereon. This deposition step results in the formation of an electrically insulating layer having an undulating surface profile, which includes at least one peak and at least one valley adjacent to the at least one peak. A non-uniform thickening step is then performed. This non-uniform thickening step includes thickening a portion of the electrically insulating layer by redepositing portions of the electrically insulating layer from the least one peak to the at least one valley. This redeposition occurs using a sputter deposition technique that utilizes the electrically insulating layer as a sputter target.

Abstract: Methods of forming integrated circuit devices include forming a field effect transistor having a gate electrode, a sacrificial spacer on a sidewall of the gate electrode and silicided source/drain regions. The sacrificial spacer is used as an implantation mask when forming highly doped portions of the source/drain regions. The sacrificial spacer is then removed from the sidewall of the gate electrode. A stress-inducing electrically insulating layer, which is configured to induce a net tensile stress (for NMOS transistors) or compressive stress (for PMOS transistors) in a channel region of the field effect transistor, is then formed on the sidewall of the gate electrode.

Abstract: Disclosed herein is a semiconducting device comprising a gate stack formed on a surface of a semiconductor substrate; a vertical nitride spacer element formed on each vertical sidewall of the gate stack; a portion of the vertical nitride spacer overlying the semiconductor substrate; a silicide contact formed on the semiconductor substrate adjacent the gate stack, the silicide contact being in operative communication with drain and source regions formed in the semiconductor substrate; and an oxide spacer disposed between the vertical nitride spacer element and the silicide contact; the oxide spacer operating to minimize an undercut adjacent the vertical nitride spacer during an etching process.

Abstract: Disclosed herein is a colorless and transparent antibiotic material including silver and a method of preparing the same. Specifically, the current invention pertains to a method of preparing a colorless and transparent antibiotic material including silver (Ag), which includes a) reacting a salt including a silver ion (Ag+) with a salt including a sulfate anion, to prepare a silver (Ag)-sulfate complex; and b) diluting the silver (Ag)-sulfate complex prepared in a) with water, and to an antibiotic material prepared using the method. Further, the current invention pertains to an antibiotic material including silver, which is harmless to the human body and exhibits disinfecting and antibiotic activities, and as well, is colorless and transparent and does not easily form colored oxides, unlike conventional silver-based antibiotic materials, and to a method of preparing such an antibiotic material.

Abstract: A trench is formed in the surface of a provided semiconductor body. An oxide is deposited in the trench and a cap is deposited on the oxide, wherein the combination of the cap and the oxide impart a mechanical stress on the semiconductor body.

Abstract: Semiconductor devices and methods of manufacturing thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a workpiece, and forming a recess in the workpiece. The recess has a depth having a first dimension. A first semiconductive material is formed in the recess to partially fill the recess in a central region to a height having a second dimension. The second dimension is about one-half or greater of the first dimension. A second semiconductive material is formed over the first semiconductive material in the recess to completely fill the recess, the second semiconductive material being different than the first semiconductive material.

Abstract: Methods of forming spacers on sidewalls of features of semiconductor devices and structures thereof are disclosed. A preferred embodiment comprises a semiconductor device including a workpiece and at least one feature disposed over the workpiece. A first spacer is disposed on the sidewalls of the at least one feature, the first spacer comprising a first material. A first liner is disposed over the first spacer and over a portion of the workpiece proximate the first spacer, the first liner comprising the first material. A second spacer is disposed over the first liner, the second spacer comprising a second material. A second liner is disposed over the second spacer, the second liner comprising the first material.

Abstract: Methods of forming integrated circuit devices include depositing an electrically insulating layer onto an integrated circuit substrate having integrated circuit structures thereon. This deposition step results in the formation of an electrically insulating layer having an undulating surface profile, which includes at least one peak and at least on valley adjacent to the at least one peak. A non-uniform thickening step is then performed. This non-uniform thickening step includes thickening a portion of the electrically insulating layer by redepositing portions of the electrically insulating layer from the least one peak to the at least one valley. This redeposition occurs using a sputter deposition technique that utilizes the electrically insulating layer as a sputter target.

Abstract: Methods of forming spacers on sidewalls of features of semiconductor devices and structures thereof are disclosed. A preferred embodiment comprises a semiconductor device including a workpiece and at least one feature disposed over the workpiece. A first spacer is disposed on the sidewalls of the at least one feature, the first spacer comprising a first material. A first liner is disposed over the first spacer and over a portion of the workpiece proximate the first spacer, the first liner comprising the first material. A second spacer is disposed over the first liner, the second spacer comprising a second material. A second liner is disposed over the second spacer, the second liner comprising the first material.

Abstract: In a method of making a semiconductor device, a recess is formed in an upper surface of the semiconductor body of a first material. An embedded semiconductor region is formed in the recess. The embedded semiconductor region is formed from a second semiconductor material that is different than the first semiconductor material. An upper surface of the embedded semiconductor region is amorphized to create an amorphous region. A silicide is then formed over the amorphous region.

Abstract: A method of forming silicide contacts for a complementary metal oxide semiconductor (CMOS) device includes selectively forming a protective layer over faceted surfaces of an embedded SiGe (eSiGe) region of a substrate, the eSiGe region comprising a compressive stress inducing layer in a PFET portion of the CMOS device, wherein the faceted surfaces are disposed adjacent shallow trench isolation (STI) regions used to separate NFET regions from PFET regions of the CMOS device; depositing a metal layer for silicide formation over the CMOS device; and annealing the CMOS device to form silicide, wherein the protective layer formed over the faceted surfaces prevents the formation of silicide thereon.

Abstract: Disclosed herein is a fluorescent light source including an yttria layer. Specifically, the current invention provides a fluorescent light source having high quality and a long lifetime, which can prevent a decrease in initial luminance of a fluorescent light source, including a fluorescent lamp, and resist the radiation of ultraviolet light and the permeation of mercury, which are the causes of deterioration of the fluorescent light source, so as not to decrease the luminance in proportion to the lighting time of the fluorescent light source, thus assuring both initial luminance properties and luminance properties after use for a long period of time. Such a fluorescent light source includes glass, a fluorescent material layer, and an absorbing layer composed mainly of yttria particles formed between the glass and the fluorescent material layer or on the inner surface of the fluorescent material layer.

Abstract: In damascene processing, metal hardmask sputtering redeposition that occurs during reactive ion etching (RIE) is exploited to produce, during the RIE process, a desired barrier metal liner on the etched feature.

Abstract: A method is provided for manufacturing a semiconductor memory device, particularly ferroelectric devices, in which an interlayer dielectric (ILD) layer formed on an upper part of a semiconductor substrate containing a capacitor structure is etched under conditions in which the plasma electron temperature is maintained in a range between 2.0 eV and 4.0 eV to open contact holes to expose the capacitor structure and thereby avoid degradation of the device characteristics.

Abstract: An improved method of manufacturing a capacitor structure for a ferroelectric random access memory (FeRAM) device on an active matrix having a first insulating layer comprising the steps of forming a buffer on the first insulating layer, a bottom electrode on the buffer, a capacitor thin film on the bottom electrode and a top electrode on the capacitor thin film. A second insulating layer is formed on the top electrode, the capacitor thin film and the first insulating layer, and then patterned and etched only once to form both a storage node contact hole and a cell plate contact hole. The capacitor structure is completed by forming a metal interconnection pattern on the second insulating layer and the contact holes to provide connection to the storage node and the cell plate.