Abstract: There is provided a method for fabricating a ferroelectric memory device, which can prevent the deterioration of the ferroelectric characteristics from etching damage generated during etching process of the interlayer-insulating layer formed over the capacitor to form a contact hole. The present invention is characterized by etching the interlayer-insulating layer with the use of time-modulated plasma, namely pulsed-power plasma. Accordingly, the present invention can prevent the deterioration of the ferroelectric characteristics from etching, omit or reduce the later separate thermal process for recovering the etching damage and enhance the reliability of device.

Abstract: There is provided a method for fabricating a ferroelectric memory device, which can prevent the deterioration of the ferroelectric characteristics from etching damage generated during etching process of the interlayer-insulating layer formed over the capacitor to form a contact hole. The present invention is characterized by etching the interlayer-insulating layer with the use of time-modulated plasma, namely pulsed-power plasma. Accordingly, the present invention can prevent the deterioration of the ferroelectric characteristics from etching, omit or reduce the later separate thermal process for recovering the etching damage and enhance the reliability of device.

Abstract: A center pillar for automobiles having a reinforcement structure, which can minimize the deformation of a center pillar against the impact occurred by a crash of vehicles is disclosed. The center pillar comprises: an inner reinforcement joined with an inner side of an inner panel for supporting said inner panel; an outer reinforcement of which an end portion is welded together with an end portion of the inner panel and an outer panel, and a first spacing portion is formed between the outer panel and the outer reinforcement; a central reinforcement joined with the one side of the outer reinforcement near to the inner reinforcement and a second spacing portion is formed between the outer reinforcement and the central reinforcement.

Abstract: A method is provided for manufacturing a semiconductor memory device, particularly ferroelectric devices, in which an interlayer dielectric (ILD) layer formed on an upper part of a semiconductor substrate containing a capacitor structure is etched under conditions in which the plasma electron temperature is maintained in a range between 2.0 eV and 4.0 eV to open contact holes to expose the capacitor structure and thereby avoid degradation of the device characteristics.

Abstract: An improved method of manufacturing a capacitor structure for a ferroelectric random access memory (FeRAM) device on an active matrix having a first insulating layer comprising the steps of forming a buffer on the first insulating layer, a bottom electrode on the buffer, a capacitor thin film on the bottom electrode and a top electrode on the capacitor thin film. A second insulating layer is formed on the top electrode, the capacitor thin film and the first insulating layer, and then patterned and etched only once to form both a storage node contact hole and a cell plate contact hole. The capacitor structure is completed by forming a metal interconnection pattern on the second insulating layer and the contact holes to provide connection to the storage node and the cell plate.

Abstract: A method for forming photoresist patterns by performing a photolithograpy process by the unit of a predetermined number of wafers, wherein the photoresist patterns are formed under a condition that an exposure time taken to fore each of the photoresist patterns is predetermined taking into consideration a variation in reflection factor, on the basis of the following equation:Z=X+{(r-a).times.(Y-X)/(.beta.-.alpha.)}where, "T" represents a reference thickness corresponding to a thickness of a photoresist film to be patterned to form a corresponding one of the photoresist patterns, exhibiting a minimum reference factor or a maximum reference factor, "T'" a thickness limit more than the reference thickness (T), ".alpha." a reference reflection factor at the reference thickness (T), ".beta." a reflection factor limit at the thickness limit (T'), "r" a varied reflection factor, "X" a reference exposure time at the reference reflection factor (.alpha.), "Y" an exposure time limit at the reflection factor limit (.

Abstract: The present invention discloses an isolation method in a semiconductor device.