Patents by Inventor Olaf Hohlfeld
Olaf Hohlfeld has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11978700Abstract: A power semiconductor module arrangement includes two or more individual semiconductor devices arranged on a base layer. Each semiconductor device includes a lead frame, a semiconductor body arranged on the lead frame, and a molding material enclosing the semiconductor body and at least part of the lead frame. A frame is arranged on the base layer such that the frame surrounds the two or more individual semiconductor devices. A casting compound at least partly fills a capacity formed by the base layer and the frame, such that the casting compound at least partly encloses the two or more individual semiconductor devices.Type: GrantFiled: July 25, 2022Date of Patent: May 7, 2024Assignee: Infineon Technologies AGInventors: Olaf Hohlfeld, Peter Kanschat
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Patent number: 11955450Abstract: A method for producing a semiconductor arrangement includes: forming a first metallization layer on a first side of a dielectric insulation layer, the first metallization layer having at least two sections, each section being separated from a neighboring section by a recess; arranging a semiconductor body on one of the sections of the first metallization layer; and forming at least one indentation between a first side of the semiconductor body and a closest edge of the respective section of the first metallization layer. A distance between the first side and the closest edge of the section of the first metallization layer is between 0.5 mm and 5 mm.Type: GrantFiled: May 2, 2023Date of Patent: April 9, 2024Assignee: Infineon Technologies AGInventor: Olaf Hohlfeld
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Publication number: 20230275059Abstract: A method for producing a semiconductor arrangement includes: forming a first metallization layer on a first side of a dielectric insulation layer, the first metallization layer having at least two sections, each section being separated from a neighboring section by a recess; arranging a semiconductor body on one of the sections of the first metallization layer; and forming at least one indentation between a first side of the semiconductor body and a closest edge of the respective section of the first metallization layer. A distance between the first side and the closest edge of the section of the first metallization layer is between 0.5 mm and 5 mm.Type: ApplicationFiled: May 2, 2023Publication date: August 31, 2023Inventor: Olaf Hohlfeld
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Patent number: 11715647Abstract: A method includes forming a first electrically conductive layer on a first side of a dielectric insulation layer, forming a structured mask layer on a side of the first electrically conductive layer that faces away from the dielectric insulation layer, forming at least one trench in the first electrically conductive layer, said at least one trench extending through the entire first electrically conductive layer to the dielectric insulation layer, forming a coating which covers at least the bottom and the side walls of the at least one trench, and removing the mask layer after the coating has been formed.Type: GrantFiled: June 9, 2021Date of Patent: August 1, 2023Assignee: Infineon Technologies AGInventors: Fabian Craes, Carsten Ehlers, Olaf Hohlfeld, Ulrich Wilke
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Patent number: 11688712Abstract: A semiconductor arrangement includes a semiconductor substrate having a dielectric insulation layer and at least a first metallization layer arranged on a first side of the dielectric insulation layer. The first metallization layer includes at least two sections, each section being separated from a neighboring section by a recess. A semiconductor body is arranged on one of the sections of the first metallization layer. At least one indentation is arranged between a first side of the semiconductor body and a closest edge of the respective section of the first metallization layer. A distance between the first side and the closest edge of the section of the first metallization layer is between 0.5 mm and 5 mm.Type: GrantFiled: February 17, 2020Date of Patent: June 27, 2023Assignee: Infineon Technologies AGInventor: Olaf Hohlfeld
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Patent number: 11610830Abstract: A power semiconductor module includes a power semiconductor chip arranged between a first substrate and a second substrate and electrically coupled to the substrates, and a temperature sensor arranged between the substrates and laterally besides the power semiconductor chip such that a first side of the temperature sensor faces the first substrate and a second side of the temperature sensor faces the second substrate. A first electrical contact of the temperature sensor is arranged on the first side and electrically coupled to the first substrate. A second electrical contact of the temperature sensor is arranged on the second side and electrically coupled to the second substrate.Type: GrantFiled: April 3, 2020Date of Patent: March 21, 2023Assignee: Infineon Technologies AGInventors: Christian Schweikert, Juergen Hoegerl, Olaf Hohlfeld, Waldemar Jakobi
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Patent number: 11557522Abstract: A method is disclosed for producing a power semiconductor module that includes a substrate, at least one semiconductor body, a connecting element and a contact element. The method includes: arranging the substrate in a housing having walls; at least partly filling a capacity formed by the walls of the housing and the substrate with an encapsulation material; hardening the encapsulation material to form a hard encapsulation; and closing the housing, wherein the contact element extends from the connecting element through an interior of the housing and through an opening in a cover of the housing to an outside of the housing in a direction perpendicular to a first surface of a first metallization layer of the substrate.Type: GrantFiled: July 2, 2021Date of Patent: January 17, 2023Assignee: Infineon Technologies AGInventors: Alexander Roth, Olaf Hohlfeld
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Publication number: 20220359365Abstract: A power semiconductor module arrangement includes two or more individual semiconductor devices arranged on a base layer. Each semiconductor device includes a lead frame, a semiconductor body arranged on the lead frame, and a molding material enclosing the semiconductor body and at least part of the lead frame. A frame is arranged on the base layer such that the frame surrounds the two or more individual semiconductor devices. A casting compound at least partly fills a capacity formed by the base layer and the frame, such that the casting compound at least partly encloses the two or more individual semiconductor devices.Type: ApplicationFiled: July 25, 2022Publication date: November 10, 2022Inventors: Olaf Hohlfeld, Peter Kanschat
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Publication number: 20220310465Abstract: A power semiconductor module includes a substrate of planar sheet metal including a plurality of islands that are each defined by channels that extend between upper and lower surfaces of the substrate, a first semiconductor die mounted on a first one of the islands, a molded body of encapsulant that covers the metal substrate, fills the channels, and encapsulates the first semiconductor die, a hole in the molded body that extends to a recess in the upper surface of the substrate, and a press-fit connector arranged in the hole such an interior end of the press-fit connector is mechanically and electrically connected to the substrate.Type: ApplicationFiled: June 16, 2022Publication date: September 29, 2022Inventors: Wu Hu Li, Raphael Hellwig, Olaf Hohlfeld, Martin Mayer, Ivan Nikitin
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Patent number: 11437311Abstract: A method for producing a power semiconductor module arrangement includes arranging two or more individual semiconductor devices on a base layer, each semiconductor device including a lead frame, a semiconductor body arranged on the lead frame, and a molding material enclosing the semiconductor body and at least part of the lead frame, arranging a frame on the base layer such that the frame surrounds the two or more individual semiconductor devices, and filling a first material into a capacity formed by the base layer and the frame, and hardening the first material to form a casting compound that at least partly fills the capacity, thereby at least partly encloses the two or more individual semiconductor devices.Type: GrantFiled: November 18, 2020Date of Patent: September 6, 2022Assignee: Infineon Technologies AGInventors: Olaf Hohlfeld, Peter Kanschat
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Patent number: 11404336Abstract: A method of forming a power semiconductor module includes providing a substrate of planar sheet metal, forming channels in an upper surface of the substrate that partially extend through a thickness of the substrate and define a plurality of islands in the substrate, mounting a first semiconductor die on a first one of the islands, forming a molded body of encapsulant that covers the substrate, fills the channels, and encapsulates the semiconductor die, forming a hole in the molded body and a recess in the upper surface of the substrate beneath the hole, and arranging a press-fit connector in the hole and forming a mechanical and electrical connection between an interior end of the press-fit connector and the substrate.Type: GrantFiled: June 29, 2020Date of Patent: August 2, 2022Assignee: Infineon Technologies Austria AGInventors: Wu Hu Li, Raphael Hellwig, Olaf Hohlfeld, Martin Mayer, Ivan Nikitin
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Patent number: 11322451Abstract: A power semiconductor module includes a power semiconductor die attached to the first metallized side, a passive component attached to the first metallized side, a first isolation layer encapsulating the power semiconductor die and the passive component, a first structured metallization layer on the first isolation layer, and a first plurality of electrically conductive vias extending through the first isolation layer from the first structured metallization layer to the power semiconductor die and the passive component.Type: GrantFiled: January 16, 2019Date of Patent: May 3, 2022Assignee: Infineon Technologies AGInventors: Olaf Hohlfeld, Juergen Hoegerl, Gottfried Beer, Magdalena Hoier, Georg Meyer-Berg
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Publication number: 20210407873Abstract: A method of forming a power semiconductor module includes providing a substrate of planar sheet metal, forming channels in an upper surface of the substrate that partially extend through a thickness of the substrate and define a plurality of islands in the substrate, mounting a first semiconductor die on a first one of the islands, forming a molded body of encapsulant that covers the substrate, fills the channels, and encapsulates the semiconductor die, forming a hole in the molded body and a recess in the upper surface of the substrate beneath the hole, and arranging a press-fit connector in the hole and forming a mechanical and electrical connection between an interior end of the press-fit connector and the substrate.Type: ApplicationFiled: June 29, 2020Publication date: December 30, 2021Inventors: Wu Hu Li, Raphael Hellwig, Olaf Hohlfeld, Martin Mayer, Ivan Nikitin
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Publication number: 20210398821Abstract: A method includes forming a first electrically conductive layer on a first side of a dielectric insulation layer, forming a structured mask layer on a side of the first electrically conductive layer that faces away from the dielectric insulation layer, forming at least one trench in the first electrically conductive layer, said at least one trench extending through the entire first electrically conductive layer to the dielectric insulation layer, forming a coating which covers at least the bottom and the side walls of the at least one trench, and removing the mask layer after the coating has been formed.Type: ApplicationFiled: June 9, 2021Publication date: December 23, 2021Inventors: Fabian Craes, Carsten Ehlers, Olaf Hohlfeld, Ulrich Wilke
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Publication number: 20210335682Abstract: A method is disclosed for producing a power semiconductor module that includes a substrate, at least one semiconductor body, a connecting element and a contact element. The method includes: arranging the substrate in a housing having walls; at least partly filling a capacity formed by the walls of the housing and the substrate with an encapsulation material; hardening the encapsulation material to form a hard encapsulation; and closing the housing, wherein the contact element extends from the connecting element through an interior of the housing and through an opening in a cover of the housing to an outside of the housing in a direction perpendicular to a first surface of a first metallization layer of the substrate.Type: ApplicationFiled: July 2, 2021Publication date: October 28, 2021Inventors: Alexander Roth, Olaf Hohlfeld
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Patent number: 11081414Abstract: A power semiconductor module arrangement includes a substrate arranged in a housing. The substrate includes a first metallization layer arranged on a first side of a dielectric insulation layer and a second metallization layer arranged on a second side of the dielectric insulation layer. At least one semiconductor body is mounted on a first surface of the first metallization layer facing away from the dielectric insulation layer. A connecting element is arranged on and electrically connected to the first surface. A contact element is inserted into and electrically connected to the connecting element, and extends from the connecting element through an interior of the housing and through an opening in the cover of the housing to an outside of the housing in a direction perpendicular to the first surface. A hard encapsulation is arranged adjacent to the first metallization layer and at least partly fills the inside of the housing.Type: GrantFiled: January 29, 2019Date of Patent: August 3, 2021Assignee: Infineon Technologies AGInventors: Alexander Roth, Olaf Hohlfeld
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Publication number: 20210074624Abstract: A method for producing a power semiconductor module arrangement includes arranging two or more individual semiconductor devices on a base layer, each semiconductor device including a lead frame, a semiconductor body arranged on the lead frame, and a molding material enclosing the semiconductor body and at least part of the lead frame, arranging a frame on the base layer such that the frame surrounds the two or more individual semiconductor devices, and filling a first material into a capacity formed by the base layer and the frame, and hardening the first material to form a casting compound that at least partly fills the capacity, thereby at least partly encloses the two or more individual semiconductor devices.Type: ApplicationFiled: November 18, 2020Publication date: March 11, 2021Inventors: Olaf Hohlfeld, Peter Kanschat
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Patent number: 10867902Abstract: A power semiconductor module arrangement including two or more individual semiconductor devices each semiconductor device having a lead frame, a semiconductor body arranged on the lead frame, and a molding material enclosing the semiconductor body and at least part of the lead frame. The power semiconductor module arrangement further includes a frame surrounding the two or more individual semiconductor devices, and a casting compound at least partly filling a capacity within the frame, thereby at least partly enclosing the two or more individual semiconductor devices.Type: GrantFiled: December 14, 2018Date of Patent: December 15, 2020Assignee: Infineon Technologies AGInventors: Olaf Hohlfeld, Peter Kanschat
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Publication number: 20200321262Abstract: A power semiconductor module includes a power semiconductor chip arranged between a first substrate and a second substrate and electrically coupled to the substrates, and a temperature sensor arranged between the substrates and laterally besides the power semiconductor chip such that a first side of the temperature sensor faces the first substrate and a second side of the temperature sensor faces the second substrate. A first electrical contact of the temperature sensor is arranged on the first side and electrically coupled to the first substrate. A second electrical contact of the temperature sensor is arranged on the second side and electrically coupled to the second substrate.Type: ApplicationFiled: April 3, 2020Publication date: October 8, 2020Inventors: Christian Schweikert, Juergen Hoegerl, Olaf Hohlfeld, Waldemar Jakobi
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Publication number: 20200266171Abstract: A semiconductor arrangement includes a semiconductor substrate having a dielectric insulation layer and at least a first metallization layer arranged on a first side of the dielectric insulation layer. The first metallization layer includes at least two sections, each section being separated from a neighboring section by a recess. A semiconductor body is arranged on one of the sections of the first metallization layer. At least one indentation is arranged between a first side of the semiconductor body and a closest edge of the respective section of the first metallization layer. A distance between the first side and the closest edge of the section of the first metallization layer is between 0.5 mm and 5 mm.Type: ApplicationFiled: February 17, 2020Publication date: August 20, 2020Inventor: Olaf Hohlfeld