Abstract: A memory address space for each of a plurality of physical memories in a microprocessor-based system is allocated prior to knowing the desired logical size of at least one of the physical memories. At least two of the allocated memory address spaces overlap at least a portion of each other. After the system is fabricated, a pointer value set that corresponds to an address boundary between at least two physical memories of the fabricated system is set during boot time and/or during run time when the size of the physical memories are known. The technique provides a faster time-to-market for microprocessor-based systems by allowing, for example, Application Specific Integrated Circuits (ASICs) comprising microprocessor systems on-chip be manufactured prior to the final firmware and software being fully developed. Additionally, the subject matter disclosed herein permits changes in memory-space allocation for finalized ASIC designs.

Abstract: A method and apparatus for overflow detection and clamping with parallel operand processing for fixed-point multipliers is disclosed. The disclosure predicts when a multiplication of a number of operands will exceed a pre-determined number of bits based upon the fixed-point format of the operands. The prediction is performed in parallel with the multiplication of the operands. The multiplication need not be completed in full, but only to the extent to determine whether overflow exists. If an overflow detection occurs, clamping is instituted. The parallel operation of the overflow detection and the multiplication provides a faster clamping circuit than would otherwise be available from a serial multiplication followed by a clamping analysis.

Abstract: A memory address space for each of a plurality of physical memories in a microprocessor-based system is allocated prior to knowing the desired logical size of at least one of the physical memories. At least two of the allocated memory address spaces overlap at least a portion of each other. After the system is fabricated, a pointer value set that corresponds to an address boundary between at least two physical memories of the fabricated system is set during boot time and/or during run time when the size of the physical memories are known. The technique provides a faster time-to-market for microprocessor-based systems by allowing, for example, Application Specific Integrated Circuits (ASICs) comprising microprocessor systems on-chip be manufactured prior to the final firmware and software being fully developed. Additionally, the subject matter disclosed herein permits changes in memory-space allocation for finalized ASIC designs.

Abstract: A method and apparatus for overflow detection and clamping with parallel operand processing for fixed-point multipliers is disclosed. The invention predicts when a multiplication of a number of operands will exceed a pre-determined number of bits based upon the fixed-point format of the operands. The prediction is performed in parallel with the multiplication of the operands. The multiplication need not be completed in full, but only to the extent to determine whether overflow exists. If an overflow detection occurs, clamping is instituted. The parallel operation of the overflow detection and the multiplication provides a faster clamping circuit than would otherwise be available from a serial multiplication followed by a clamping analysis.

Abstract: A flexible architecture is presented that allows either Synchronous Optical Network (SONET) framing, Optical Transport Network (OTN) framing, or SONET framing followed by OTN framing. The architecture consists of SONET frame processors, OTN frame processors, and a configurable selection network.

Abstract: A method and apparatus for overflow detection and clamping with parallel operand processing for fixed-point multipliers is disclosed. The invention predicts when a multiplication of a number of operands will exceed a pre-determined number of bits based upon the fixed-point format of the operands. The prediction is performed in parallel with the multiplication of the operands. The multiplication need not be completed in full, but only to the extent to determine whether overflow exists. If an overflow detection occurs, clamping is instituted. The parallel operation of the overflow detection and the multiplication provides a faster clamping circuit than would otherwise be available from a serial multiplication followed by a clamping analysis.

Abstract: A method and apparatus for overflow detection and clamping with parallel operand processing for fixed-point multipliers is disclosed. The invention predicts when a multiplication of a number of operands will exceed a pre-determined number of bits based upon the fixed-point format of the operands. The prediction is performed in parallel with the multiplication of the operands. The multiplication need not be completed in full, but only to the extent to determine whether overflow exists. If an overflow detection occurs, clamping is instituted. The parallel operation of the overflow detection and the multiplication provides a faster clamping circuit than would otherwise be available from a serial multiplication followed by a clamping analysis.

Abstract: A texture addressing circuit and method for calculating texture coordinates according to various texture addressing modes for texture maps having arbitrary sizes. Texture coordinates are calculated from input texture coordinate values the texture addressing circuit receives and that are located in one of a plurality of predefined input ranges. The texture addressing circuit includes a plurality of coordinate calculation circuits to calculate coordinate output values for each of the input coordinate ranges and to provide the values to a selection circuit from which an output texture coordinate is selected. An output texture coordinate is selected based on the sign of the input texture coordinate and the sign of the calculated texture coordinate values.

Abstract: A plurality of cache addressing functions are stored in main memory. A processor which executes a program selects one of the stored cache addressing functions for use in a caching operation during execution of a program by the processor.

Abstract: A method and apparatus for computing a level-of detail (LOD) value for the of texels of a texture map to pixels of a graphics image adapted to receive signals representing texel coordinates for texels of a texture map and pixel coordinates for pixels of a graphics image to calculate a level-of-detail (LOD). The apparatus computes the LOD by calculating the square of the ratio between the number of texels applied to one pixel from the texel and pixel coordinates, approximating a base-two logarithm of the square of the ratio, and dividing the result of the approximation by two to compute the LOD.

Abstract: FIFO queues enable multiple accesses to data stored therein. A release pointer points to a queue location containing previously read data until a release signal is asserted that changes the release pointer while a read pointer is used to read data from the queue. The repeat signal allows the read pointer to reread previously read data. Asserting the repeat signal sets the read pointer to the value of the release pointer. Once data is no longer needed, the release signal is asserted, causing the release pointer to be incremented with the read pointer thereby freeing memory locations. FIFO queues may comprise multiple release pointers, multiple release and multiple repeat signals. FIFO queues may also comprise a switch signal, which causes the read pointer to switch values with a release pointer. FIFO queues may comprise multiple read pointers and an input signal for determining which read pointer is used.

Abstract: A plurality of cache addressing functions are stored in main memory. A processor which executes a program selects one of the stored cache addressing functions for use in a caching operation during execution of a program by the processor.

Abstract: A plurality of cache addressing functions are stored in main memory. A processor which executes a program selects one of the stored cache addressing functions for use in a caching operation during execution of a program by the processor.

Abstract: Linear interpolators that are both accurate and cost effective to implement in hardware are presented. These interpolators use a multi-bit value approach that permits adders to be used instead of multipliers. The inherent error known in multi-bit value approaches is corrected by using a more accurate approximation for a distance ratio used in interpolation calculations.

Abstract: A flexible architecture is presented that allows either Synchronous Optical Network (SONET) framing, Optical Transport Network (OTN) framing, or SONET framing followed by OTN framing. The architecture consists of SONET frame processors, OTN frame processors, and a configurable selection network.

Abstract: FIFO queues enable multiple accesses to data stored therein. A release pointer points to a queue location containing previously read data until a release signal is asserted that changes the release pointer while a read pointer is used to read data from the queue. The repeat signal allows the read pointer to reread previously read data. Asserting the repeat signal sets the read pointer to the value of the release pointer. Once data is no longer needed, the release signal is asserted, causing the release pointer to be incremented with the read pointer thereby freeing memory locations. FIFO queues may comprise multiple release pointers, multiple release and multiple repeat signals. FIFO queues may also comprise a switch signal, which causes the read pointer to switch values with a release pointer. FIFO queues may comprise multiple read pointers and an input signal for determining which read pointer is used.

Abstract: FIFO queues are provided that enable multiple accesses to data stored in the FIFO queue. Conventional FIFO queues can be augmented by the addition of a “release pointer,” a “repeat signal,” and a “release signal.” A release pointer points to a location in the queue containing a data element that has already been read. As long as the release signal is not asserted, the release pointer does not change while a read pointer is used to read data from the queue. In order to allow the read pointer to go back and reread previously read data, the repeat signal can be asserted. Asserting the repeat signal causes the read pointer to be set to the value of the release pointer. Once the data is no longer needed, the release pointer can be asserted; causing the release pointer to be incremented along with the read pointer. Incrementing the release pointer frees up memory locations so that new data can be stored in them.

Abstract: FIFO queues are provided that enable multiple accesses to data stored in the FIFO queue. Conventional FIFO queues can be augmented by the addition of a “release pointer,” a “repeat signal,” and a “release signal.” A release pointer points to a location in the queue containing a data element that has already been read. As long as the release signal is not asserted, the release pointer does not change while a read pointer is used to read data from the queue. In order to allow the read pointer to go back and reread previously read data, the repeat signal can be asserted. Asserting the repeat signal causes the read pointer to be set to the value of the release pointer. Once the data is no longer needed, the release pointer can be asserted, causing the release pointer to be incremented along with the read pointer. Incrementing the release pointer frees up memory locations so that new data can be stored in them.

Abstract: A plurality of cache addressing functions are stored in main memory. A processor which executes a program selects one of the stored cache addressing functions for use in a caching operation during execution of a program by the processor.

Abstract: Linear interpolators that are both accurate and cost effective to implement in hardware are presented. These interpolators use a multi-bit value approach that permits adders to be used instead of multipliers. The inherent error known in multi-bit value approaches is corrected by using a more accurate approximation for a distance ratio used in interpolation calculations.