Abstract: An electronic system and method that maintains time dependencies and ordering constraints in an electronic system. A timing controller utilizes a representative bit to track timing dependencies associated with information and ensures the information is communicated and processed in an order that preserves the timing dependencies as the information is converted from parallel to parallel or parallel to serial operations. The present invention tracks the order in which information is loaded in a electronic hardware component and ensures that the information loaded into the electronic hardware component at a particular time is processed without interruption by information loaded at a different time.

Abstract: A method of a computer graphics system recirculates texture cache misses into a graphics pipeline without stalling the graphics pipeline, increasing the processing speed of the computer graphics system. The method reads data from a texture cache memory by a read request placed in the graphics pipeline sequence, then reads the data from the texture cache memory if the data is stored in the texture cache memory and places the data in the pipeline sequence. If the data is not stored in the texture cache memory, the method recirculates the read request in the pipeline sequence by indicating in the pipeline sequence that the data is not stored in the texture cache memory, placing the read request at a subsequent, determined place in the pipeline sequence, reading the data into the texture cache memory from a main memory, and executing the read request from the subsequent, determined place and after the data has been read into the texture cache memory.

Abstract: The present invention pertains to an apparatus for and method of mapping texture memory to a texture cache such that cache contention is minimized. Significantly, in one embodiment of the present invention, addresses of the texture memory are mapped to entries of the texture cache according to a predetermined hashing scheme. According to the one embodiment, texture memory is addressed as a virtually contiguous address space by a multi-dimensional index. The multi-dimensional index is further partitioned into a low order bit field and a high order bit field. Low order bits of the multi-dimensional index are directly mapped to low order bits of the cache address. High order bits of the multi-dimensional index are mapped to high order bits of the cache address according to a predetermined address-hashing scheme. Particularly, in one embodiment, high order bits of the multi-dimensional index are selectively “exclusive-or-ed” to generate corresponding addresses of the texture cache.