Abstract: A receiver circuit includes a first circuit having two modes of operation controlled by a feedback loop. The feedback loop is connected to an output of the first circuit, and the modes of operation include a first mode having a quicker response to an input falling signal edge than a second mode and a second mode with a quicker response to an input rising signal edge than the first mode. A driver stage is integrated into the first circuit to favor the rising edge or the falling edge in accordance with a control signal provided by the feedback loop.

Abstract: A receiver circuit provides a first stage having an input for receiving input signals and an output node. The first stage includes an amplifier. A second stage has an input coupled to the output of the first stage. The second stage includes a switching circuit coupled to the output node of the first stage for driving the input signals by favoring a rising edge or a falling edge in accordance with a control signal. The second stage also includes a feedback loop coupled to an output of the second stage. The feedback loop provides the control signal for switching the switching circuit to favor the rising edge or falling edge.

Abstract: A delay lock loop, in accordance with the present invention, includes a plurality of phase detectors each receiving a first clock signal and a second clock signal. Each phase detector includes a specified delay range for detecting phase differences between the first and second clock signals in that range. A delay line includes an input and an output. The first clock signal is received at the input, and the second clock signal includes a delayed first clock signal. An amount of delay is applied to the first clock signal, which is adjusted in the delay line in accordance with control signals of the phase detectors.

Abstract: Dynamic random access memory chips (DRAMs) in a computer memory system are made to be more available for access by a processor even though an autorefresh cycle may be in progress when the processor attempts to access the memory system. A DECODED AUTOREFRESH mode is defined which allows refresh of certain banks of the DRAM only. The bank addresses from the external DRAM controller select the bank where the AUTOREFRESH has to be performed. The DRAM controller circuitry makes sure that every bank of the DRAM gets a refresh command often enough to retain information.

Abstract: A clock circuit, in accordance with the present invention, includes a first circuit stage for providing a first output signal and a second output signal. The first circuit stage includes inputs for clock signals. A switch is coupled to the first stage for switching an output polarity by selecting one of the first output signal and the second output signal generated by the first circuit stage in accordance with a control signal. A second circuit stage is coupled to the first circuit stage through the switch. The second circuit stage for shaping the first and second output signals input thereto from the switch. The second circuit stage includes an output for outputting clock pulses based on the first and second output signals. The control signal is generated from the clock pulses.

Abstract: A receiver circuit, in accordance with the present invention, includes a first stage having an input for receiving input signals and an output node. The first stage includes an amplifier, and a second stage includes an input coupled to the output of the first stage. The second stage also includes a logic gate coupled to the output of the first stage, the logic gate having an output representing the output of the receiver circuit, and a feed back element coupled from the logic gate output and connecting to a switching element. The switching element, being responsive to the logic gate output, switches a current source on and off to adjust a switchpoint of the receiver circuit.

Abstract: Dynamic random access memory chips (DRAMs) in a computer memory system are made to be more available for access by a processor even though an autorefresh cycle may be in progress when the processor attempts to access the memory system. A DECODED AUTOREFRESH mode is defined which allows refresh of certain banks of the DRAM only. The bank addresses from the external DRAM controller select the bank where the AUTOREFRESH has to be performed. The DRAM controller circuitry makes sure that every bank of the DRAM gets a refresh command often enough to retain information.

Abstract: A sensing system for sensing data from a data source and driving a pair of output lines in response thereto comprises: a primary sensing device operatively coupled to the data source for sensing and storing said data therein; and a secondary sensing device operatively coupled to the primary sensing device via a pair of input lines and also operatively coupled to the pair of output lines, the secondary sensing device being responsive to a differential voltage generated across the pair of input lines in accordance with said data stored by the primary sensing device and the secondary sensing device having a differential voltage threshold range associated therewith defined by a negative threshold and a positive threshold, whereby the secondary sensing device drives the pair of output lines to a first output condition when the differential voltage across the pair of input lines is within the differential voltage threshold range, to a second output condition when the differential voltage is at least equal to the ne

Abstract: A semiconductor memory device is disclosed which includes an input terminal for receiving, and an output terminal for producing a data word, each having a predetermined number of bits. An internal memory array stores a plurality of error correcting encoded codewords each encoding more than one data word. An error correcting encoder is coupled between the input terminal and the memory array for generating an error correcting encoded codeword, encoding the received data word, and storing the codeword in the internal memory array. An error correcting decoder is coupled between the internal memory array and the output terminal to retrieve an error correction encoded codeword from the internal memory array, correct any detected errors, and produce one of the more than one data words encoded in the retrieved codeword at the output terminal.

Abstract: Testing of a multibank memory device having a plurality of memory banks which includes activating two or more of the plurality of memory banks for participation in the test; selecting at least one common memory address corresponding to a memory cell within each activated bank; simultaneously writing test data into the selected memory cell of each activated bank; simultaneously reading the test data previously written into the selected memory cell of each activated bank; and comparing the test data read from each activated bank with the test data from each other activated bank and if a match is determined to exist, then indicating a pass condition, else indicating a fail condition.

Abstract: A fully differential resistor-string digital-to-analog converter wherein a resistor network having half the number of resistors of an otherwise standard digital-to-analog convertor of this type is enabled with the assistance of a first decoder, a second decoder and a subtraction unit thus reducing the required chip area and the overall switching time.

Abstract: A redundant circuit configuration for an integrated semiconductor memory has normal and redundant memory cells, in which addresses of arbitrary groups of memory cells of the memory are formed from a first partial address and a second partial address. M fixedly programmable address circuits, where M.gtoreq.1, are each assigned to one of the first partial addresses. Each fixedly programmable address circuit in an activated state has the second partial address of a group of normal memory cells to be replaced and has a first output at which an activation signal is applied in the activated state of the address circuit if the first partial address applied to the circuit configuration matches the first partial address assigned to the address circuit. One address comparator is common to all of the address circuits and has a first output.

Abstract: A current mirror includes first through eighteenth transistors. The load paths of the first and second transistors are in series for carrying an input current to a first supply potential. The control terminals of the first through eighth transistors receive the input current. The load paths of the fourth, third, ninth and tenth transistors are in series between the first and a second supply potential. The third and ninth transistors form a tap being connected to the control terminals of the ninth, tenth, eleventh, twelfth and thirteenth transistors. The load paths of the fifth, sixth, eleventh and fourteenth transistors are in series between the first and second supply potentials. The sixth and eleventh transistors form a tap being connected to the control terminals of the fourteenth through sixteenth transistors. The load paths of the seventeenth, seventh, twelfth and fifteenth transistors are in series between the first and second supply potentials.

Abstract: A current mirror includes first and second transistors each having a control terminal and a load path with two terminals. The control terminals of the first and second transistors and one of the terminals of the load path of the first transistor receive a first input current. Third, fourth and fifth transistors each have a control terminal and a load path with two terminals. The control terminals of the third, fourth and fifth transistors and one of the terminals of the load path of the third transistor receive a second input current of equal magnitude to the first input current. One of the terminals of the load path of the fifth transistor supplies an output current proportional to the two input currents. The other of the terminals of the load paths of the third and fifth transistors are each connected to one terminal of the load path of a respective one of the fourth and second transistors.

Abstract: A circuit configuration for adjusting the quadrature-axis current component of a push-pull output stage has two transistors of opposed conduction type and is triggered by an input signal. A variable being proportional to the quadrature-axis current component of the push-pull output stage is derived from a comparison circuit. A final control element adjusts the quadrature-axis current components of the push-pull output stage and of the comparison circuit for matching the variable to a reference variable.

Abstract: A decoded source sense amplifier in which the column select signal is shaped so that it turns on bit select transistors at a predetermined time after the source electrodes of the sense amplifier are connected to ground, so as to give the sense amplifier time to latch before it is coupled to external bit lines.

Abstract: A fuse, having reduced blow-current requirements thereby minimizing the power supply voltage and chip area required for the driver transistors, has a geometry which is characterized by an essentially uniform width dimension throughout the primary axis of the fuse link but having at least one approximately right angle bend in the fuse link. The fuse can be blown open with approximately 10% of the input current density required for a straight fuse of equal cross-sectional area. The reason for this is that, due to current crowding, the current density is accentuated at the inside corner of the bend. As the input current to the fuse is increased, a current density is reached at the inside corner which causes the fuse material to melt. A notch forms at the inside corner. The fuse geometry altered by the notching causes even more severe current crowding at the notches, and this in turn makes the melting propagate across the width of the fuse.