Patents by Inventor Olivier Joubert
Olivier Joubert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230352264Abstract: Systems and methods for creating arbitrarily-shaped ion energy distribution functions using shaped-pulse-bias. In an embodiment, a method includes applying a negative jump voltage to an electrode of a process chamber to set a wafer voltage for a wafer, modulating an amplitude of the wafer voltage to produce a train of groups of pulse bursts with different amplitudes, and repeating the modulating of the amplitude of the wafer voltage to repeat the train of the groups of pulse bursts to create an ion energy distribution function having more than one energy peak. In some embodiments, the negative jump voltage can include a single-cycle voltage waveform with a voltage ramp during an ion-current phase, in which the voltage ramp can be positive or negative and a duration of the ion-current phase can comprise more or less than fifty percent of a period of the waveform.Type: ApplicationFiled: July 11, 2023Publication date: November 2, 2023Applicant: Applied Materials, Inc.Inventors: Leonid DORF, Travis KOH, Olivier LUERE, Olivier JOUBERT, Philip A. KRAUS, Rajinder DHINDSA, James ROGERS
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Patent number: 11728124Abstract: Systems and methods for creating arbitrarily-shaped ion energy distribution functions using shaped-pulse-bias. In an embodiment, a method includes applying a positive jump voltage to an electrode of a process chamber to neutralize a wafer surface, applying a negative jump voltage to the electrode to set a wafer voltage, and modulating the amplitude of the wafer voltage to produce a predetermined number of pulses to determine an ion energy distribution function. In another embodiment a method includes applying a positive jump voltage to an electrode of a process chamber to neutralize a wafer surface, applying a negative jump voltage to the electrode to set a wafer voltage, and applying a ramp voltage to the electrode that overcompensates for ion current on the wafer or applying a ramp voltage to the electrode that undercompensates for ion current on the wafer.Type: GrantFiled: July 16, 2021Date of Patent: August 15, 2023Assignee: APPLIED MATERIALS, INC.Inventors: Leonid Dorf, Travis Koh, Olivier Luere, Olivier Joubert, Philip A. Kraus, Rajinder Dhindsa, James Rogers
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Patent number: 11208354Abstract: The present invention relates to a zirconia mullite refractory composite comprising 55 wt.-% to 65 wt.-% Al2O3, 15 wt.-% to 25 wt.-% SiO2, 15 wt.-% to 25 wt.-% ZrO2 and less than 3 wt.-% raw material based impurities, whereby the mineralogical composition of the composite comprises 65 wt.-% to 85 wt.-% mullite and 15 wt.-% to 35 wt.-% zirconia.Type: GrantFiled: November 3, 2016Date of Patent: December 28, 2021Assignee: ImerTech SASInventors: Marie-Laure Bouchetou, Olivier Joubert, Jacques Poirier, Michael Weissenbacher
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Publication number: 20210343496Abstract: Systems and methods for creating arbitrarily-shaped ion energy distribution functions using shaped-pulse-bias. In an embodiment, a method includes applying a positive jump voltage to an electrode of a process chamber to neutralize a wafer surface, applying a negative jump voltage to the electrode to set a wafer voltage, and modulating the amplitude of the wafer voltage to produce a predetermined number of pulses to determine an ion energy distribution function. In another embodiment a method includes applying a positive jump voltage to an electrode of a process chamber to neutralize a wafer surface, applying a negative jump voltage to the electrode to set a wafer voltage, and applying a ramp voltage to the electrode that overcompensates for ion current on the wafer or applying a ramp voltage to the electrode that undercompensates for ion current on the wafer.Type: ApplicationFiled: July 16, 2021Publication date: November 4, 2021Inventors: LEONID DORF, TRAVIS KOH, OLIVIER LUERE, OLIVIER JOUBERT, PHILIP A. KRAUS, RAJINDER DHINDSA, JAMES ROGERS
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Patent number: 11069504Abstract: Systems and methods for creating arbitrarily-shaped ion energy distribution functions using shaped-pulse—bias. In an embodiment, a method includes applying a positive jump voltage to an electrode of a process chamber to neutralize a wafer surface, applying a negative jump voltage to the electrode to set a wafer voltage, and modulating the amplitude of the wafer voltage to produce a predetermined number of pulses to determine an ion energy distribution function. In another embodiment a method includes applying a positive jump voltage to an electrode of a process chamber to neutralize a wafer surface, applying a negative jump voltage to the electrode to set a wafer voltage, and applying a ramp voltage to the electrode that overcompensates for ion current on the wafer or applying a ramp voltage to the electrode that undercompensates for ion current on the wafer.Type: GrantFiled: May 5, 2020Date of Patent: July 20, 2021Assignee: APPLIED MATERIALS, INC.Inventors: Leonid Dorf, Travis Koh, Olivier Luere, Olivier Joubert, Philip A. Kraus, Rajinder Dhindsa, James Rogers
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Patent number: 11049760Abstract: The implementations described herein generally relate to a process kit suitable for use in a semiconductor process chamber, which reduces edge effects and widens the processing window with a single edge ring as compared to conventional process kits. The process kit generally includes an edge ring disposed adjacent to and surrounding a perimeter of a semiconductor substrate in a plasma chamber. A dimension of a gap between the substrate and the edge ring is less than about 1000 ?m, and a height difference between the substrate and the edge ring is less than about (+/?) 300 ?m. The resistivity of the ring is less than about 50 Ohm-cm.Type: GrantFiled: February 20, 2017Date of Patent: June 29, 2021Assignee: Applied Materials, Inc.Inventors: Olivier Joubert, Jason A. Kenney, Sunil Srinivasan, James Rogers, Rajinder Dhindsa, Vedapuram S. Achutharaman, Olivier Luere
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Publication number: 20200266022Abstract: Systems and methods for creating arbitrarily-shaped ion energy distribution functions using shaped-pulse—bias. In an embodiment, a method includes applying a positive jump voltage to an electrode of a process chamber to neutralize a wafer surface, applying a negative jump voltage to the electrode to set a wafer voltage, and modulating the amplitude of the wafer voltage to produce a predetermined number of pulses to determine an ion energy distribution function. In another embodiment a method includes applying a positive jump voltage to an electrode of a process chamber to neutralize a wafer surface, applying a negative jump voltage to the electrode to set a wafer voltage, and applying a ramp voltage to the electrode that overcompensates for ion current on the wafer or applying a ramp voltage to the electrode that undercompensates for ion current on the wafer.Type: ApplicationFiled: May 5, 2020Publication date: August 20, 2020Inventors: LEONID DORF, TRAVIS KOH, OLIVIER LUERE, OLIVIER JOUBERT, PHILIP A. KRAUS, RAJINDER DHINDSA, JAMES ROGERS
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Patent number: 10685807Abstract: Systems and methods for creating arbitrarily-shaped ion energy distribution functions using shaped-pulse-bias. In an embodiment, a method includes applying a positive jump voltage to an electrode of a process chamber to neutralize a wafer surface, applying a negative jump voltage to the electrode to set a wafer voltage, and modulating the amplitude of the wafer voltage to produce a predetermined number of pulses to determine an ion energy distribution function. In another embodiment a method includes applying a positive jump voltage to an electrode of a process chamber to neutralize a wafer surface, applying a negative jump voltage to the electrode to set a wafer voltage, and applying a ramp voltage to the electrode that overcompensates for ion current on the wafer or applying a ramp voltage to the electrode that undercompensates for ion current on the wafer.Type: GrantFiled: May 7, 2019Date of Patent: June 16, 2020Assignee: APPLIED MATERIALS, INC.Inventors: Leonid Dorf, Travis Koh, Olivier Luere, Olivier Joubert, Philip A. Kraus, Rajinder Dhindsa, James Rogers
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Publication number: 20190259562Abstract: Systems and methods for creating arbitrarily-shaped ion energy distribution functions using shaped-pulse-bias. In an embodiment, a method includes applying a positive jump voltage to an electrode of a process chamber to neutralize a wafer surface, applying a negative jump voltage to the electrode to set a wafer voltage, and modulating the amplitude of the wafer voltage to produce a predetermined number of pulses to determine an ion energy distribution function. In another embodiment a method includes applying a positive jump voltage to an electrode of a process chamber to neutralize a wafer surface, applying a negative jump voltage to the electrode to set a wafer voltage, and applying a ramp voltage to the electrode that overcompensates for ion current on the wafer or applying a ramp voltage to the electrode that undercompensates for ion current on the wafer.Type: ApplicationFiled: May 7, 2019Publication date: August 22, 2019Inventors: LEONID DORF, TRAVIS KOH, OLIVIER LUERE, OLIVIER JOUBERT, PHILIP A. KRAUS, RAJINDER DHINDSA, JAMES ROGERS
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Patent number: 10312048Abstract: Systems and methods for creating arbitrarily-shaped ion energy distribution functions using shaped-pulse-bias. In an embodiment, a method includes applying a positive jump voltage to an electrode of a process chamber to neutralize a wafer surface, applying a negative jump voltage to the electrode to set a wafer voltage, and modulating the amplitude of the wafer voltage to produce a predetermined number of pulses to determine an ion energy distribution function. In another embodiment a method includes applying a positive jump voltage to an electrode of a process chamber to neutralize a wafer surface, applying a negative jump voltage to the electrode to set a wafer voltage, and applying a ramp voltage to the electrode that overcompensates for ion current on the wafer or applying a ramp voltage to the electrode that undercompensates for ion current on the wafer.Type: GrantFiled: December 7, 2017Date of Patent: June 4, 2019Assignee: APPLIED MATERIALS, INC.Inventors: Leonid Dorf, Travis Koh, Olivier Luere, Olivier Joubert, Philip A. Kraus, Rajinder Dhindsa, James Hugh Rogers
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Publication number: 20190043697Abstract: A ring assembly for a substrate support is disclosed herein. The ring assembly has a ring shaped body. The ring shaped body has an inner diameter and an outer diameter, a top surface, an inner portion at the inner diameter, and an outer portion at the outer diameter. A carbon based coating is disposed on the top surface of the ring shaped body, wherein the carbon based coating is thicker on the inner portion of the ring shaped body than the outer portion of the ring shaped body.Type: ApplicationFiled: October 10, 2018Publication date: February 7, 2019Inventors: Olivier JOUBERT, Olivier LUERE, Vedapuram S. ACHUTHARAMAN
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Publication number: 20180327314Abstract: The present invention relates to a zirconia mullite refractory composite comprising 55 wt.-% to 65 wt.-% Al2O3, 15 wt.-% to 25 wt.-% SiO2, 15 wt.-% to 25 wt.-% ZrO2 and less than 3 wt.-% raw material based impurities, whereby the mineralogical composition of the composite comprises 65 wt.-% to 85 wt.-% mullite and 15 wt.-% to 35 wt.-% zirconia.Type: ApplicationFiled: November 3, 2016Publication date: November 15, 2018Inventors: Marie-Laure BOUCHETOU, Olivier JOUBERT, Jacques POIRIER, Michael WEISSENBACHER
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Patent number: 10109464Abstract: Methods are disclosed for etching a substrate. The method includes preferentially coating cover ring relative other chamber components in the processing chamber, while under vacuum, and while a substrate is not present in the processing chamber. The substrate is subsequently etched the processing chamber. After etching, the interior of the processing chamber is cleaned after the substrate has been removed.Type: GrantFiled: October 26, 2016Date of Patent: October 23, 2018Assignee: Applied Materials, Inc.Inventors: Olivier Joubert, Olivier Luere, Vedapuram S. Achutharaman
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Patent number: 10062602Abstract: The invention relates to a method of etching a layer of porous dielectric material, characterized in that the etching is performed in a plasma formed from at least one silicon-based gas mixed with oxygen (O2) and/or nitrogen (N2) so as to grow a passivation layer all along said etching, at least on flanks of the layer of porous dielectric material and wherein the silicon-based gas is taken from all the compounds of the type SixHy for which the ratio x/y is equal or greater than 0.3 or is taken from all the compounds of the following types: SixFy and SixCly, where x is the proportion of silicon (Si) in the gas and y is the proportion of fluorine (F) or chlorine (Cl) or hydrogen (H) in the gas.Type: GrantFiled: December 27, 2013Date of Patent: August 28, 2018Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, CNRS—Centre National de la Recherche Scientifique, APPLIED MATERIALS, IncInventors: Nicolas Posseme, Sebastien Barnola, Olivier Joubert, Srinivas Nemani, Laurent Vallier
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Patent number: 10056266Abstract: A method for manufacturing a resistive device, includes depositing a first electrically conductive layer on a substrate; forming an etching mask on the first conductive layer; etching the first conductive layer through the mask, such as to obtain a plurality of electrically conductive pillars separated from one another; and forming storage elements with variable electrical resistance at the tops of the electrically conductive pillars, such that each storage element is supported by one of the electrically conductive pillars, the step of forming the storage elements including the following operations depositing a first layer by non-collimated cathode sputtering at normal incidence relative to the substrate; and depositing a second layer on the first layer by cathode sputtering, the second layer including a first chemical species sputtered at an oblique incidence.Type: GrantFiled: October 15, 2015Date of Patent: August 21, 2018Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE (CNRS), UNIVERSITE GRENOBLE ALPESInventors: Bernard Dieny, Maxime Darnon, Gabriele Navarro, Olivier Joubert
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Publication number: 20180166249Abstract: Systems and methods for creating arbitrarily-shaped ion energy distribution functions using shaped-pulse-bias. In an embodiment, a method includes applying a positive jump voltage to an electrode of a process chamber to neutralize a wafer surface, applying a negative jump voltage to the electrode to set a wafer voltage, and modulating the amplitude of the wafer voltage to produce a predetermined number of pulses to determine an ion energy distribution function. In another embodiment a method includes applying a positive jump voltage to an electrode of a process chamber to neutralize a wafer surface, applying a negative jump voltage to the electrode to set a wafer voltage, and applying a ramp voltage to the electrode that overcompensates for ion current on the wafer or applying a ramp voltage to the electrode that undercompensates for ion current on the wafer.Type: ApplicationFiled: December 7, 2017Publication date: June 14, 2018Inventors: Leonid DORF, Travis KOH, Olivier LUERE, Olivier JOUBERT, Philip A. KRAUS, Rajinder DHINDSA, JAMES HUGH ROGERS
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Patent number: 9975758Abstract: Embodiments include devices and methods for detecting particles, monitoring etch or deposition rates, or controlling an operation of a wafer fabrication process. In an embodiment, one or more micro sensors are mounted on wafer processing equipment, and are capable of measuring material deposition and removal rates in real-time. The micro sensors are selectively exposed such that a sensing layer of a micro sensor is protected by a mask layer during active operation of another micro sensor, and the protective mask layer may be removed to expose the sensing layer when the other micro sensor reaches an end-of-life. Other embodiments are also described and claimed.Type: GrantFiled: July 13, 2017Date of Patent: May 22, 2018Assignee: Applied Materials, Inc.Inventors: Leonard Tedeschi, Lili Ji, Olivier Joubert, Dmitry Lubomirsky, Philip Allan Kraus, Daniel T. McCormick
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Publication number: 20180057356Abstract: Embodiments include devices and methods for detecting particles, monitoring etch or deposition rates, or controlling an operation of a wafer fabrication process. In an embodiment, one or more micro sensors are mounted on wafer processing equipment, and are capable of measuring material deposition and removal rates in real-time. The micro sensors are selectively exposed such that a sensing layer of a micro sensor is protected by a mask layer during active operation of another micro sensor, and the protective mask layer may be removed to expose the sensing layer when the other micro sensor reaches an end-of-life. Other embodiments are also described and claimed.Type: ApplicationFiled: July 13, 2017Publication date: March 1, 2018Inventors: Leonard Tedeschi, Lili Ji, Olivier Joubert, Dmitry Lubomirsky, Philip Allan Kraus, Daniel T. McCormick
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Patent number: 9818621Abstract: Embodiments described herein relate to methods for etching a substrate. Patterning processes, such as double patterning and quadruple patterning processes, may benefit from the embodiments described herein which include performing an inert plasma treatment to implant ions into a spacer material, performing an etching process on an implanted region of the spacer material, and repeating the inert plasma treatment and the etching process to form a predominantly flat top spacer profile. The inert plasma treatment process may be a biased process and the etching process may be an unbiased process. Various processing parameters, such as pressure, may be controlled to influence a desired spacer profile.Type: GrantFiled: January 4, 2017Date of Patent: November 14, 2017Assignee: APPLIED MATERIALS, INC.Inventors: Aurelien Tavernier, Qingjun Zhou, Tom Choi, Yungchen Lin, Ying Zhang, Olivier Joubert
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Publication number: 20170309497Abstract: A method for manufacturing a resistive device, includes depositing a first electrically conductive layer on a substrate; forming an etching mask on the first conductive layer; etching the first conductive layer through the mask, such as to obtain a plurality of electrically conductive pillars separated from one another; and forming storage elements with variable electrical resistance at the tops of the electrically conductive pillars, such that each storage element is supported by one of the electrically conductive pillars, the step of forming the storage elements including the following operations depositing a first layer by non-collimated cathode sputtering at normal incidence relative to the substrate; and depositing a second layer on the first layer by cathode sputtering, the second layer including a first chemical species sputtered at an oblique incidence.Type: ApplicationFiled: October 15, 2015Publication date: October 26, 2017Inventors: Bernard DIENY, Maxime DARNON, Gabriele NAVARRO, Olivier JOUBERT