Patents by Inventor Omkaram Nalamasu

Omkaram Nalamasu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11011676
    Abstract: Fabrication of gallium nitride-based light devices with physical vapor deposition (PVD)-formed aluminum nitride buffer layers is described. Process conditions for a PVD AlN buffer layer are also described. Substrate pretreatments for a PVD aluminum nitride buffer layer are also described. In an example, a method of fabricating a buffer layer above a substrate involves pre-treating a surface of a substrate. The method also involves, subsequently, reactive sputtering an aluminum nitride (AlN) layer on the surface of the substrate from an aluminum-containing target housed in a physical vapor deposition (PVD) chamber with a nitrogen-based gas or plasma.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: May 18, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Mingwei Zhu, Rongjun Wang, Nag B. Patibandla, Xianmin Tang, Vivek Agrawal, Cheng-Hsiung Tsai, Muhammad Rasheed, Dinesh Saigal, Praburam Gopal Raja, Omkaram Nalamasu, Anantha Subramani
  • Patent number: 9911582
    Abstract: The present disclosure provides methods and an apparatus for controlling and modifying line width roughness (LWR) of a photoresist layer with enhanced electron spinning control. In one embodiment, an apparatus for controlling a line width roughness of a photoresist layer disposed on a substrate includes a processing chamber having a chamber body having a top wall, side wall and a bottom wall defining an interior processing region, a support pedestal disposed in the interior processing region of the processing chamber, and a plasma generator source disposed in the processing chamber operable to provide predominantly an electron beam source to the interior processing region.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: March 6, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Banqiu Wu, Ajay Kumar, Kartik Ramaswamy, Omkaram Nalamasu
  • Publication number: 20180047980
    Abstract: Disclosed are a cathode active material for a lithium secondary battery, and a lithium secondary battery including the same. The disclosed cathode active material includes a core including a compound represented by Formula 1; and a shell including a compound represented by Formula 2, in which the core and the shell have different material compositions.
    Type: Application
    Filed: October 20, 2017
    Publication date: February 15, 2018
    Inventors: BYUNG-SUNG LEO KWAK, JOSEPH G. GORDON, II, OMKARAM NALAMASU, YANGKOOK SUN, WONGI KIM, SEUNGMIN OH
  • Publication number: 20160293798
    Abstract: Fabrication of gallium nitride-based light devices with physical vapor deposition (PVD)-formed aluminum nitride buffer layers is described. Process conditions for a PVD AlN buffer layer are also described. Substrate pretreatments for a PVD aluminum nitride buffer layer are also described. In an example, a method of fabricating a buffer layer above a substrate involves pre-treating a surface of a substrate. The method also involves, subsequently, reactive sputtering an aluminum nitride (AlN) layer on the surface of the substrate from an aluminum-containing target housed in a physical vapor deposition (PVD) chamber with a nitrogen-based gas or plasma.
    Type: Application
    Filed: June 15, 2016
    Publication date: October 6, 2016
    Inventors: Mingwei Zhu, Rongjun Wang, Nag B. Patibandla, Xianmin Tang, Vivek Agrawal, Cheng-Hsiung Tsai, Muhammad Rasheed, Dinesh Saigal, Praburam Gopal Raja, Omkaram Nalamasu, Anantha Subramani
  • Patent number: 9396933
    Abstract: Fabrication of gallium nitride-based light devices with physical vapor deposition (PVD)-formed aluminum nitride buffer layers is described. Process conditions for a PVD AlN buffer layer are also described. Substrate pretreatments for a PVD aluminum nitride buffer layer are also described. In an example, a method of fabricating a buffer layer above a substrate involves pre-treating a surface of a substrate. The method also involves, subsequently, reactive sputtering an aluminum nitride (AlN) layer on the surface of the substrate from an aluminum-containing target housed in a physical vapor deposition (PVD) chamber with a nitrogen-based gas or plasma.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: July 19, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Mingwei Zhu, Rongjun Wang, Nag B. Patibandia, Xianmin Tang, Vivek Agrawal, Cheng-Hsiung Tsai, Muhammad Rasheed, Dinesh Saigal, Praburam Gopal Raja, Omkaram Nalamasu, Anantha Subramani
  • Patent number: 9350040
    Abstract: Methods of and factories for thin-film battery manufacturing are described. A method includes operations for fabricating a thin-film battery. A factory includes one or more tool sets for fabricating a thin-film battery.
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: May 24, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Byung-Sung Kwak, Stefan Bangert, Dieter Haas, Omkaram Nalamasu
  • Patent number: 9280051
    Abstract: Methods for reducing line width roughness and/or critical dimension nonuniformity in a photoresist pattern are provided herein. In some embodiments, a method of reducing line width roughness along a sidewall of a patterned photoresist layer disposed atop a substrate includes: (a) depositing a first layer atop the sidewall of the patterned photoresist layer; (b) etching the first layer and the sidewall after depositing the first layer to reduce the line width roughness of the patterned photoresist layer. In some embodiments, (a)-(b) may be repeated until the line width roughness is substantially smooth.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: March 8, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Banqiu Wu, Ajay Kumar, Rao Yalamanchili, Omkaram Nalamasu
  • Publication number: 20160064197
    Abstract: The present disclosure provides methods and an apparatus for controlling and modifying line width roughness (LWR) of a photoresist layer with enhanced electron spinning control. In one embodiment, an apparatus for controlling a line width roughness of a photoresist layer disposed on a substrate includes a processing chamber having a chamber body having a top wall, side wall and a bottom wall defining an interior processing region, a support pedestal disposed in the interior processing region of the processing chamber, and a plasma generator source disposed in the processing chamber operable to provide predominantly an electron beam source to the interior processing region.
    Type: Application
    Filed: November 12, 2015
    Publication date: March 3, 2016
    Inventors: Banqiu WU, Ajay KUMAR, Kartik RAMASWAMY, Omkaram NALAMASU
  • Patent number: 9263078
    Abstract: A method for patterning a magnetic thin film on a substrate includes: providing a pattern about the magnetic thin film, with selective regions of the pattern permitting penetration of energized ions of one or more elements. Energized ions are generated with sufficient energy to penetrate selective regions and a portion of the magnetic thin film adjacent the selective regions. The substrate is placed to receive the energized ions. The portions of the magnetic thin film are rendered to exhibit a magnetic property different than selective other portions. A method for patterning a magnetic media with a magnetic thin film on both sides of the media is also disclosed.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: February 16, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Steven Verhaverbeke, Omkaram Nalamasu, Majeed A. Foad, Mahalingam Venkatesan, Nety M. Krishna
  • Patent number: 9177824
    Abstract: Methods for reducing the line width roughness on a photoresist pattern are provided herein. In some embodiments, a method of processing a patterned photoresist layer disposed atop a substrate includes flowing a process gas into a processing volume of a process chamber having the substrate disposed therein; forming a plasma within the process chamber from the process gas, wherein the plasma has a ion energy of about 1 eV to about 10 eV; and etching the patterned photoresist layer with species from the plasma to at least one of smooth a line width roughness of a sidewall of the patterned photoresist layer or remove debris.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: November 3, 2015
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Banqiu Wu, Ajay Kumar, Leonid Dorf, Shahid Rauf, Kartik Ramaswamy, Omkaram Nalamasu
  • Patent number: 9130238
    Abstract: Methods of and hybrid factories for thin-film battery manufacturing are described. A method includes operations for fabricating a thin-film battery. A hybrid factory includes one or more tool sets for fabricating a thin-film battery.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: September 8, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Byung-Sung Kwak, Stefan Bangert, Dieter Haas, Omkaram Nalamasu
  • Patent number: 9105921
    Abstract: Embodiments of the present invention generally relate to methods and apparatus for forming an energy storage device. More particularly, embodiments described herein relate to methods of forming electric batteries and electrochemical capacitors. In one embodiment a method of forming a high surface area electrode for use in an energy storage device is provided. The method comprises forming an amorphous silicon layer on a current collector having a conductive surface, immersing the amorphous silicon layer in an electrolytic solution to form a series of interconnected pores in the amorphous silicon layer, and forming carbon nanotubes within the series of interconnected pores of the amorphous silicon layer.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: August 11, 2015
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Victor L. Pushparaj, Omkaram Nalamasu, Steven Verhaverbeke
  • Patent number: 8962224
    Abstract: Methods for providing a silicon layer on a photomask substrate surface with minimum defeats for fabricating film stack thereon for EUVL applications are provided. In one embodiment, a method for forming a silicon layer on a photomask substrate includes performing an oxidation process to form a silicon oxide layer on a surface of a first substrate wherein the first substrate comprises a crystalline silicon material, performing an ion implantation process to define a cleavage plane in the first substrate, and bonding the silicon oxide layer to a surface of a second substrate, wherein the second substrate is a quartz photomask.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: February 24, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Banqiu Wu, Ajay Kumar, Omkaram Nalamasu
  • Patent number: 8932802
    Abstract: Methods and apparatus for performing an atomic layer deposition lithography process are provided in the present disclosure. In one embodiment, a method for forming features on a material layer in a device includes pulsing a first reactant gas mixture to a surface of a substrate disposed in a processing chamber to form a first monolayer of a material layer on the substrate surface, directing an energetic radiation to treat a first region of the first monolayer, and pulsing a second reactant gas mixture to the substrate surface to selectively form a second monolayer on a second region of the first monolayer.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: January 13, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Banqiu Wu, Ajay Kumar, Omkaram Nalamasu
  • Publication number: 20140370708
    Abstract: Methods for reducing the line width roughness on a photoresist pattern are provided herein. In some embodiments, a method of processing a patterned photoresist layer disposed atop a substrate includes flowing a process gas into a processing volume of a process chamber having the substrate disposed therein; forming a plasma within the process chamber from the process gas, wherein the plasma has a ion energy of about 1 eV to about 10 eV; and etching the patterned photoresist layer with species from the plasma to at least one of smooth a line width roughness of a sidewall of the patterned photoresist layer or remove debris.
    Type: Application
    Filed: June 11, 2014
    Publication date: December 18, 2014
    Inventors: BANQIU WU, AJAY KUMAR, LEONID DORF, SHAHID RAUF, KARTIK RAMASWAMY, OMKARAM NALAMASU
  • Publication number: 20140370709
    Abstract: Methods for reducing line width roughness and/or critical dimension nonuniformity in a photoresist pattern are provided herein. In some embodiments, a method of reducing line width roughness along a sidewall of a patterned photoresist layer disposed atop a substrate includes: (a) depositing a first layer atop the sidewall of the patterned photoresist layer; (b) etching the first layer and the sidewall after depositing the first layer to reduce the line width roughness of the patterned photoresist layer. In some embodiments, (a)-(b) may be repeated until the line width roughness is substantially smooth.
    Type: Application
    Filed: June 11, 2014
    Publication date: December 18, 2014
    Inventors: BANQIU WU, AJAY KUMAR, RAO YALAMANCHILI, OMKARAM NALAMASU
  • Publication number: 20140356768
    Abstract: Embodiments of the present invention generally provide an apparatus and methods for etching photomasks using charged beam plasma. In one embodiment, an apparatus for performing a charged beam plasma process on a photomask includes a processing chamber having a chamber bottom, a chamber ceiling and chamber sidewalls defining an interior volume, a substrate support pedestal disposed in the interior volume, a charged beam generation system disposed adjacent to the chamber sidewall, and a RF bias electrode disposed in the substrate support.
    Type: Application
    Filed: May 29, 2013
    Publication date: December 4, 2014
    Inventors: Banqiu WU, Ajay KUMAR, Amitabh SABHARWAL, Leonid DORF, Ming-Feng WU, Shahid RAUF, Kartik RAMASWAMY, Kenneth S. COLLINS, Omkaram NALAMASU
  • Publication number: 20140342229
    Abstract: Disclosed are a cathode active material for a lithium secondary battery, and a lithium secondary battery including the same. The disclosed cathode active material includes a core including a compound represented by Formula 1; and a shell including a compound represented by Formula 2, in which the core and the shell have different material compositions.
    Type: Application
    Filed: December 12, 2012
    Publication date: November 20, 2014
    Inventors: Byung-Sung Leo Kwak, Joseph G. Gordon, II, Omkaram Nalamasu, Yangkook Sun, Wongi Kim, Seugmin Oh
  • Patent number: 8846437
    Abstract: Embodiments of the invention provide a method of forming a doped gallium arsenide based (GaAs) layer from a solution based precursor. The doped gallium arsenide based (GaAs) layer formed from the solution based precursor may assist solar cell devices to improve light absorption and conversion efficiency. In one embodiment, a method of forming a solar cell device includes forming a first layer with a first type of dopants doped therein over a surface of a substrate, forming a GaAs based layer on the first layer, and forming a second layer with a second type of dopants doped therein on the GaAs based layer.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: September 30, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Kaushal K. Singh, Robert Jan Visser, Srikant Rao, Bhaskar Kumar, Claire J. Carmalt, Ranga Rao Arnepalli, Omkaram Nalamasu, Gaurav Saraf, Sanjayan Sathasivam, Christopher Stuart Blackman
  • Publication number: 20140178728
    Abstract: A method of fabricating an energy storage device with a large surface area electrode comprises: providing an electrically conductive substrate; depositing a semiconductor layer on the electrically conductive substrate, the semiconductor layer being a first electrode; anodizing the semiconductor layer, wherein the anodization forms pores in the semiconductor layer, increasing the surface area of the first electrode; after the anodization, providing an electrolyte and a second electrode to form the energy storage device. The substrate may be a continuous film and the electrode of the energy storage device may be fabricated using linear processing tools. The semiconductor may be silicon and the deposition tool may be a thermal spray tool. Furthermore, the semiconductor layer may be amorphous. The energy storage device may be rolled into a cylindrical shape. The energy storage device may be a battery, a capacitor or an ultracapacitor.
    Type: Application
    Filed: February 26, 2014
    Publication date: June 26, 2014
    Applicant: Applied Materials, Inc.
    Inventors: Omkaram NALAMASU, Steven VERHAVERBEKE