Patents by Inventor Osamu Tsuchiya

Osamu Tsuchiya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6592649
    Abstract: The present invention provides a method of producing metallic iron nuggets with a high yield and good productivity, and more particularly a method which can produce metallic iron nuggets which have a high Fe purity and are excellent in transporting and handling due to a large grain diameter with a high yield and good productivity, when they are produced by reducing and melting raw material containing iron oxide such as iron ore and carbonaceous reducing agent such as coke.
    Type: Grant
    Filed: June 28, 2001
    Date of Patent: July 15, 2003
    Assignee: Midrex International B.V. Zurich Branch
    Inventors: Shoichi Kikuchi, Yasuhiro Tanigaki, Koji Tokuda, Osamu Tsuchiya, Shuzo Ito
  • Patent number: 6579505
    Abstract: A method for producing an iron oxide pellet including the steps of adding water to a raw material mixture comprising iron oxide which serves as a primary component, a carbonaceous material in an amount sufficient for reducing the iron oxide, an organic binder in an amount sufficient for binding the iron oxide and the carbonaceous material, and an inorganic coagulant in an amount of not less than 0.05 mass % and less than 1 mass %; pelletizing the resultant mixture to thereby obtain a green pellet; and drying the green pellet until the moisture content is reduced to equal to or less than 1.0 mass %. The thus-produced iron oxide pellet is charged in a reducing furnace for reduction to thereby obtain a reduced iron pellet.
    Type: Grant
    Filed: July 11, 2002
    Date of Patent: June 17, 2003
    Assignee: Kabushiki Kaisha Kobe Seiko Sho
    Inventors: Osamu Tsuchiya, Hidetoshi Tanaka, Takao Harada, Jun Jimbo, Shoichi Kikuchi, Yasuhiko Igawa
  • Patent number: 6567311
    Abstract: A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and lightening the burden imposed on software for use in additional writing. The data stored in a designated sector is read out before being saved in a register, and the selected sector is subjected to single-sector erasing when a predetermined command is given. Then write expected value data is formed from the saved data and data to be additionally written, completing the writing operation.
    Type: Grant
    Filed: March 13, 2002
    Date of Patent: May 20, 2003
    Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.
    Inventors: Tatsuya Ishii, Hitoshi Miwa, Osamu Tsuchiya, Shooji Kubono
  • Patent number: 6548847
    Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel s
    Type: Grant
    Filed: July 9, 2001
    Date of Patent: April 15, 2003
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Jun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane
  • Publication number: 20030061909
    Abstract: A method of making metallic iron in which a compact, containing iron oxide such as iron ore or the like and a carbonaceous reductant such as coal or the like, is used as material, and the iron oxide is reduced through the application of heat, thereby making metallic iron. In the course of this reduction, a shell composed of metallic iron is generated and grown on the surface of the compact, and slag aggregates inside the shell. This reduction continues until substantially no iron oxide is present within the metallic iron shell. Subsequently, heating is further performed to melt the metallic iron and slag. Molten metallic iron and molten slag are separated one from the other, thereby obtaining metallic iron with a relatively high metallization ratio.
    Type: Application
    Filed: November 7, 2002
    Publication date: April 3, 2003
    Applicant: KABUSHIKI KAISHA KOBE SEIKO SHO
    Inventors: Takuya Negami, Kazuo Kunii, Shinichi Inaba, Masataka Shimizu, Isao Kobayashi, Yoshimichi Takenaka, Toshihide Matsumura, Akira Uragami, Takashi Kujirai, Osamu Tsuchiya, Kimio Sugiyama, Shuzo Ito, Shoichi Kikuchi
  • Patent number: 6506231
    Abstract: A method of making metallic iron in which a compact, containing iron oxide such as iron ore or the like and a carbonaceous reductant such as coal or the like, is used as material, and the iron oxide is reduced through the application of heat, thereby making metallic iron. In the course of this reduction, a shell composed of metallic iron is generated and grown on the surface of the compact, and slag aggregates inside the shell. This reduction continues until substantially no iron oxide is present within the metallic iron shell. Subsequently, heating is further performed to melt the metallic iron and slag. Molten metallic iron and molten slag are separated one from the other, thereby obtaining metallic iron with a relatively high metallization ratio.
    Type: Grant
    Filed: June 26, 2001
    Date of Patent: January 14, 2003
    Assignee: Kabushiki Kaisha Kobe Seiko Sho
    Inventors: Takuya Negami, Kazuo Kunii, Shinichi Inaba, Masataka Shimizu, Isao Kobayashi, Yoshimichi Takenaka, Toshihide Matsumura, Akira Uragami, Takashi Kujirai, Osamu Tsuchiya, Kimio Sugiyama, Shuzo Ito, Shoichi Kikuchi
  • Patent number: 6498100
    Abstract: In a method of manufacturing a semiconductor device having a memory mat portion in which an active region and a field region are formed densely, after a polishing stopper film is deposited on a semiconductor substrate, there are formed grooves by etching a polishing stopper film of a field region and the semiconductor substrate. Then, after an insulating film is deposited so as to fill the grooves, then insulating film is partly removed from the memory mat portion by etching. Under this state, the insulating film is chemically mechanically polished until the polishing stopper film is exposed. The film thickness of the polishing stopper film on the active region can be reduced, and an electrical element isolation characteristic of the field region can be improved.
    Type: Grant
    Filed: November 30, 2001
    Date of Patent: December 24, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Akio Nishida, Kikuo Kusukawa, Toshiaki Yamanaka, Natsuki Yokoyama, Shinichiro Kimura, Norio Suzuki, Osamu Tsuchiya, Atsushi Ogishima
  • Publication number: 20020175441
    Abstract: A method for producing an iron oxide pellet including the steps of adding water to a raw material mixture comprising iron oxide which serves as a primary component, a carbonaceous material in an amount sufficient for reducing the iron oxide, an organic binder in an amount sufficient for binding the iron oxide and the carbonaceous material, and an inorganic coagulant in an amount of not less than 0.05 mass % and less than 1 mass %; pelletizing the resultant mixture to thereby obtain a green pellet; and drying the green pellet until the moisture content is reduced to equal to or less than 1.0 mass %. The thus-produced iron oxide pellet is charged in a reducing furnace for reduction to thereby obtain a reduced iron pellet.
    Type: Application
    Filed: July 11, 2002
    Publication date: November 28, 2002
    Applicant: KABUSHIKI KAISHA KOBE SEIKO SHO
    Inventors: Osamu Tsuchiya, Hidetoshi Tanaka, Takao Harada, Jun Jimbo, Shoichi Kikuchi, Yasuhiko Igawa
  • Publication number: 20020136056
    Abstract: A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and lightening the burden imposed on software for use in additional writing. The data stored in a designated sector is read out before being saved in a register, and the selected sector is subjected to single-sector erasing when a predetermined command is given. Then write expected value data is formed from the saved data and data to be additionally written, completing the writing operation.
    Type: Application
    Filed: March 13, 2002
    Publication date: September 26, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Tatsuya Ishii, Hitoshi Miwa, Osamu Tsuchiya, Shooji Kubono
  • Patent number: 6452838
    Abstract: A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and lightening the burden imposed on software for use in additional writing. The data stored in a designated sector is read out before being saved in a register, and the selected sector is subjected to single-sector erasing when a predetermined command is given. Then write expected value data is formed from the saved data and data to be additionally written, completing the writing operation.
    Type: Grant
    Filed: November 27, 2001
    Date of Patent: September 17, 2002
    Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.
    Inventors: Tatsuya Ishii, Hitoshi Miwa, Osamu Tsuchiya, Shooji Kubono
  • Patent number: 6442070
    Abstract: A nonvolatile semiconductor memory device is provided which includes a plurality of memory cells each having a floating gate, wherein a threshold level of each memory cell depends on a value of electric charge in said floating gate of said memory cell, and wherein said threshold level of each memory cell is placed at one of a first area and a second area. A controller is also provided which controls to set each threshold voltage of selected ones of said plurality of memory cells, wherein said controller performs a first setting operation and a verifying operation. The first setting operation shifts threshold voltages of the selected ones of said plurality of memory cells in a direction from said first area to said second area. The verifying operation detects erratic memory cells which have threshold voltages which are on a side of said second area which is opposite of a middle area formed between the first area and the second area.
    Type: Grant
    Filed: October 10, 2000
    Date of Patent: August 27, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Toshihiro Tanaka, Masataka Kato, Osamu Tsuchiya, Toshiaki Nishimoto
  • Patent number: 6432533
    Abstract: A method of making metallic iron in which a compact, containing iron oxide such as iron ore or the like and a carbonaceous reductant such as coal or the like, is used as material, and the iron oxide is reduced through the application of heat, thereby making metallic iron. In the course of this reduction, a shell composed of metallic iron is generated and grown on the surface of the compact, and slag aggregates inside the shell. This reduction continues until substantially no iron oxide is present within the metallic iron shell. Subsequently, heating is further performed to melt the metallic iron and slag. Molten metallic iron and molten slag are separated one from the other, thereby obtaining metallic iron with a relatively high metallization ratio.
    Type: Grant
    Filed: January 6, 2000
    Date of Patent: August 13, 2002
    Assignee: Kabushiki Kaisha Kobe Seiko Sho
    Inventors: Takuya Negami, Kazuo Kunii, Shinichi Inaba, Masataka Shimizu, Isao Kobayashi, Yoshimichi Takenaka, Toshihide Matsumura, Akira Uragami, Takashi Kujirai, Osamu Tsuchiya, Kimio Sugiyama, Shuzo Ito, Shoichi Kikuchi
  • Patent number: 6392932
    Abstract: A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and lightening the burden imposed on software for use in additional writing. The data stored in a designated sector is read out before being saved in a register, and the selected sector is subjected to single-sector erasing when a predetermined command is given. Then write expected value data is formed from the saved data and data to be additionally written, completing the writing operation.
    Type: Grant
    Filed: November 17, 2000
    Date of Patent: May 21, 2002
    Inventors: Tatsuya Ishii, Hitoshi Miwa, Osamu Tsuchiya, Shooji Kubono
  • Publication number: 20020055261
    Abstract: In a method of manufacturing a semiconductor device having a memory mat portion in which an active region and a field region are formed densely, after a polishing stopper film is deposited on a semiconductor substrate, there are formed grooves by etching a polishing stopper film of a field region and the semiconductor substrate. Then, after an insulating film is deposited so as to fill the grooves, then insulating film is partly removed from the memory mat portion by etching. Under this state, the insulating film is chemically mechanically polished until the polishing stopper film is exposed. The film thickness of the polishing stopper film on the active region can be reduced, and an electrical element isolation characteristic of the field region can be improved.
    Type: Application
    Filed: November 30, 2001
    Publication date: May 9, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Akio Nishida, Kikuo Kusukawa, Toshiaki Yamanaka, Natsuki Yokoyama, Shinichiro Kimura, Norio Suzuki, Osamu Tsuchiya, Atsushi Ogishima
  • Publication number: 20020054511
    Abstract: A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and lightening the burden imposed on software for use in additional writing. The data stored in a designated sector is read out before being saved in a register, and the selected sector is subjected to single-sector erasing when a predetermined command is given. Then write expected value data is formed from the saved data and data to be additionally written, completing the writing operation.
    Type: Application
    Filed: November 27, 2001
    Publication date: May 9, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Tatsuya Ishii, Hitoshi Miwa, Osamu Tsuchiya, Shooji Kubono
  • Patent number: 6385092
    Abstract: A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and lightening the burden imposed on software for use in additional writing. The data stored in a designated sector is read out before being saved in a register, and the selected sector is subjected to single-sector erasing when a predetermined command is given. Then write expected value data is formed from the saved data and data to be additionally written, completing the writing operation.
    Type: Grant
    Filed: September 25, 2001
    Date of Patent: May 7, 2002
    Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.
    Inventors: Tatsuya Ishii, Hitoshi Miwa, Osamu Tsuchiya, Shooji Kubono
  • Patent number: 6380085
    Abstract: In a method of manufacturing a semiconductor device having a memory mat portion in which an active region and a field region are formed densely, after a polishing stopper film is deposited on a semiconductor substrate, there are formed grooves by etching a polishing stopper film of a field region and the semiconductor substrate. Then, after an insulating film is deposited so as to fill the grooves, then insulating film is partly removed from the memory mat portion by etching. Under this state, the insulating film is chemically mechanically polished until the polishing stopper film is exposed. The film thickness of the polishing stopper film on the active region can be reduced, and an electrical element isolation characteristic of the field region can be improved.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: April 30, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Akio Nishida, Kikuo Kusukawa, Toshiaki Yamanaka, Natsuki Yokoyama, Shinichiro Kimura, Norio Suzuki, Osamu Tsuchiya, Atsushi Ogishima
  • Publication number: 20020033075
    Abstract: The present invention provides a method of producing metallic iron nuggets with a high yield and good productivity, and more particularly a method which can produce metallic iron nuggets which have a high Fe purity and are excellent in transporting and handling due to a large grain diameter with a high yield and good productivity, when they are produced by reducing and melting raw material containing iron oxide such as iron ore and carbonaceous reducing agent such as coke.
    Type: Application
    Filed: June 28, 2001
    Publication date: March 21, 2002
    Applicant: MIDREX INTERNATIONAL B.V.
    Inventors: Shoichi Kikuchi, Yasuhiro Tanigaki, Koji Tokuda, Osamu Tsuchiya, Shuzo Ito
  • Publication number: 20020034099
    Abstract: A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and lightening the burden imposed on software for use in additional writing. The data stored in a designated sector is read out before being saved in a register, and the selected sector is subjected to single-sector erasing when a predetermined command is given. Then write expected value data is formed from the saved data and data to be additionally written, completing the writing operation.
    Type: Application
    Filed: September 25, 2001
    Publication date: March 21, 2002
    Applicant: Hitaci, Ltd.
    Inventors: Tatsuya Ishii, Hitoshi Miwa, Osamu Tsuchiya, Shooji Kubono
  • Publication number: 20020017669
    Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel s
    Type: Application
    Filed: July 9, 2001
    Publication date: February 14, 2002
    Inventors: Jun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane