Patents by Inventor Otto Torreiter
Otto Torreiter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9620244Abstract: Embodiments of the present invention provide methods, program products, and systems for testing a memory cell arrangement. Embodiments of the present invention can determine categories of memory fail conditions by checking memory cells of with a sequence of test parameter configurations for a malfunction using test parameters, storing for test parameter configurations for which a malfunction is detected, and assigning the respective test parameter configuration with a bit fail count comprising the number of malfunctioning memory cells. Embodiments of the present invention can be used to create a relational data structure representing test parameter configurations and can combine one or more test parameter configurations and can create a representation of the bit fail counts of the respective test parameter configurations.Type: GrantFiled: May 10, 2016Date of Patent: April 11, 2017Assignee: International Business Machines CorporationInventors: Martin Eckert, Nils Schlemminger, Otto A. Torreiter
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Publication number: 20170092377Abstract: Embodiments of the present invention provide systems and methods for a RAM at speed flexible timing and setup control. The memory module includes: a module connected to a functional logic circuitry; first timing control latches of a first scan-in chain; a timing configuration circuitry controllable by timing and control configuration signals; selection circuits connected to each output line of the first timing control latches; and an output signal of the timing configuration circuitry is connected to input lines of the selection circuits, such that two sets of control data are operatively connected to the control input lines of the memory cells under test, without a reloading of the respective timing control latches.Type: ApplicationFiled: October 30, 2015Publication date: March 30, 2017Inventors: Martin Eckert, Michael B. Kugel, Otto A. Torreiter, Tobias Werner
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Publication number: 20170092341Abstract: Embodiments of the present invention provide systems and methods for a RAM at speed flexible timing and setup control. The memory module includes: a module connected to a functional logic circuitry; first timing control latches of a first scan-in chain; a timing configuration circuitry controllable by timing and control configuration signals; selection circuits connected to each output line of the first timing control latches; and an output signal of the timing configuration circuitry is connected to input lines of the selection circuits, such that two sets of control data are operatively connected to the control input lines of the memory cells under test, without a reloading of the respective timing control latches.Type: ApplicationFiled: September 24, 2015Publication date: March 30, 2017Inventors: Martin Eckert, Michael B. Kugel, Otto A. Torreiter, Tobias Werner
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Patent number: 9496188Abstract: A method for soldering three-dimensional integrated circuits is provided. A three-dimensional integrated circuit is heated to a base temperature, wherein the base temperature is lower than the melting point of a solder, and wherein the three-dimensional integrated circuit includes a plurality of solder bumps. A first on-chip heat source reflows a first portion of the plurality of solder bumps that is within a first local-hot-zone. A second on-chip heat source reflows a second portion of the plurality of solder bumps that is within a second local-hot-zone.Type: GrantFiled: March 30, 2015Date of Patent: November 15, 2016Assignee: International Business Machines CorporationInventors: Martin Eckert, Eckhard Kunigkeit, Otto A. Torreiter, Quintino L. Trianni
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Publication number: 20160293497Abstract: A method for soldering three-dimensional integrated circuits is provided. A three-dimensional integrated circuit is heated to a base temperature, wherein the base temperature is lower than the melting point of a solder, and wherein the three-dimensional integrated circuit includes a plurality of solder bumps. A first on-chip heat source reflows a first portion of the plurality of solder bumps that is within a first local-hot-zone. A second on-chip heat source reflows a second portion of the plurality of solder bumps that is within a second local-hot-zone.Type: ApplicationFiled: March 30, 2015Publication date: October 6, 2016Inventors: Martin Eckert, Eckhard Kunigkeit, Otto A. Torreiter, Quintino L. Trianni
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Patent number: 9401222Abstract: Embodiments of the present invention provide methods, program products, and systems for testing a memory cell arrangement. Embodiments of the present invention can determine categories of memory fail conditions by checking memory cells of with a sequence of test parameter configurations for a malfunction using test parameters, storing for test parameter configurations for which a malfunction is detected, and assigning the respective test parameter configuration with a bit fail count comprising the number of malfunctioning memory cells. Embodiments of the present invention can be used to create a relational data structure representing test parameter configurations and can combine one or more test parameter configurations and can create a representation of the bit fail counts of the respective test parameter configurations.Type: GrantFiled: November 23, 2015Date of Patent: July 26, 2016Assignee: International Business Machines CorporationInventors: Martin Eckert, Nils Schlemminger, Otto A. Torreiter
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Patent number: 9322848Abstract: A semiconductor die with an array of contacts, where at least two contacts in adjacent positions have the same data signal during testing operations with a test probe. The adjacent contacts of the cluster allow the use of a larger test probe tip and/or greater tolerance on test probe tip alignment during testing operations.Type: GrantFiled: July 3, 2013Date of Patent: April 26, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Otto A. Torreiter, Dieter Wendel
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Publication number: 20160097807Abstract: A method for electrical testing of a 3-D integrated circuit chip stack is described. The 3-D integrated circuit chip stack comprises at least a first integrated circuit chip and a second integrated circuit chip. The first integrated circuit chip and the second integrated circuit chip are not soldered together for performing electrical testing.Type: ApplicationFiled: December 10, 2015Publication date: April 7, 2016Inventors: Martin ECKERT, Eckhard KUNIGKEIT, Otto A. TORREITER, Quintino L. TRIANNI
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Patent number: 9250289Abstract: A method for electrical testing of a 3-D integrated circuit chip stack is described. The 3-D integrated circuit chip stack comprises at least a first integrated circuit chip and a second integrated circuit chip. The first integrated circuit chip and the second integrated circuit chip are not soldered together for performing electrical testing.Type: GrantFiled: November 18, 2013Date of Patent: February 2, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Martin Eckert, Eckhard Kunigkeit, Otto A. Torreiter, Quintino L. Trianni
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Patent number: 9217758Abstract: A method of testing a semiconductor die having an array of contacts, where at least two I/O pads in adjacent positions have the same data signal during testing operations with a test probe. The adjacent I/O pads form a test cluster allowing the use of a larger test probe tip and/or greater tolerance on test probe tip alignment during testing operations.Type: GrantFiled: January 28, 2014Date of Patent: December 22, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Otto A. Torreiter, Dieter Wendel
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Patent number: 9094306Abstract: Network power fault detection. At least one first network device is instructed to temporarily disconnect from a power supply path of a network, and at least one characteristic of the power supply path of the network is measured at a second network device connected to the network while the at least one first network device is temporarily disconnected from the network.Type: GrantFiled: June 7, 2013Date of Patent: July 28, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Martin Eckert, Roland Frech, Claudio Siviero, Jochen Supper, Otto A. Torreiter, Thomas-Michael Winkel
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Publication number: 20150201537Abstract: A chip attach frame is used to align pins of an integrated circuit chip with pads on a chip carrier. A frame block has a socket defining two alignment edges that form a reference corner. The chip is lowered into the socket, and the chip carrier is inclined while it supports the frame block and chip until the chip moves under force of gravity to the reference corner. Once located at the reference corner, the chip position is carefully adjusted by moving the frame block in the x- and y-directions until the pins are aligned with the pads. The frame block is spring biased against movement in the x- and y-directions, and the position of the frame block is adjusted using thumbscrews. A plunger mechanism can be used to secure the integrated circuit chip in forcible engagement with the chip carrier once the pins are aligned with the pads.Type: ApplicationFiled: September 4, 2013Publication date: July 16, 2015Applicant: International Business Machines CorporationInventors: Martin Eckert, Otto Torreiter, Quintino L. Trianni
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Publication number: 20150162097Abstract: The invention relates to a method for performing an array built-in self-test (ABIST) on an electronic circuit (100), the electronic circuit (100) comprising a memory (110) with at least two memory arrays (111-115) and at least two array built-in self-test engines (116-120), wherein each automatic built-in self-test engine (116-120) is associated with a different memory array (111-115) and wherein each array built-in self-test engine (116-120) is associated with a programmable delay unit (DU1-DU5), the method comprising the following steps: determine at least one delay value (dn), the delay value (dn) corresponding to an array built-in self-test engine (116-120) and the delay value (dn) depending on the execution time (tdn) for testing the memory array (111-115) associated with the array built-in self-test engine (116-120); provide the at least one delay value (dn) to the programmable delay unit (DU1-DU5); and delay the start of the array built-in self-test engine (116-120) depending on the respective delay vType: ApplicationFiled: October 29, 2014Publication date: June 11, 2015Inventors: Martin Eckert, Otto Torreiter, Christian Zoelin
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Publication number: 20150059166Abstract: A chip attach frame is used to align pins of an integrated circuit chip with pads on a chip carrier. A frame block has a socket defining two alignment edges that form a reference corner. The chip is lowered into the socket, and the chip carrier is inclined while it supports the frame block and chip until the chip moves under force of gravity to the reference corner. Once located at the reference corner, the chip position is carefully adjusted by moving the frame block in the x- and y-directions until the pins are aligned with the pads. The frame block is spring biased against movement in the x- and y-directions, and the position of the frame block is adjusted using thumbscrews. A plunger mechanism can be used to secure the integrated circuit chip in forcible engagement with the chip carrier once the pins are aligned with the pads.Type: ApplicationFiled: September 4, 2013Publication date: March 5, 2015Applicant: International Business Machines CorporationInventors: Martin Eckert, Otto Torreiter, Quintino L. Trianni
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Publication number: 20150008949Abstract: A semiconductor die with an array of contacts, where at least two contacts in adjacent positions have the same data signal during testing operations with a test probe. The adjacent contacts of the cluster allow the use of a larger test probe tip and/or greater tolerance on test probe tip alignment during testing operations.Type: ApplicationFiled: July 3, 2013Publication date: January 8, 2015Inventors: Otto A. Torreiter, Dieter Wendel
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Publication number: 20150008947Abstract: A method of testing a semiconductor die having an array of contacts, where at least two I/O pads in adjacent positions have the same data signal during testing operations with a test probe. The adjacent I/O pads form a test cluster allowing the use of a larger test probe tip and/or greater tolerance on test probe tip alignment during testing operations.Type: ApplicationFiled: January 28, 2014Publication date: January 8, 2015Applicant: International Business Machines CorporationInventors: Otto A. Torreiter, Dieter Wendel
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Patent number: 8866504Abstract: A system for measuring a test voltage level (Vx) in a location within a chip is presented. The system includes an on-chip measurement device with an on-chip comparator and an on-chip storage. The on-chip comparator is configured for comparing the test voltage (Vx) to be measured to a reference voltage (Vref), while the on-chip storage is configured for storing the result of this comparison. The system also includes external (off-chip) equipment for generating the reference voltage (Vref), for generating probe signals for probing the state of the storage and for retrieving the state of said on-chip storage.Type: GrantFiled: October 25, 2011Date of Patent: October 21, 2014Assignee: International Business Machines CorporationInventors: Martin Eckert, Roland Frech, Otto Torreiter, Dieter Wendel
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Publication number: 20140300382Abstract: A method for electrical testing of a 3-D integrated circuit chip stack is described. The 3-D integrated circuit chip stack comprises at least a first integrated circuit chip and a second integrated circuit chip. The first integrated circuit chip and the second integrated circuit chip are not soldered together for performing electrical testing.Type: ApplicationFiled: November 18, 2013Publication date: October 9, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Martin ECKERT, Eckhard KUNIGKEIT, Otto A. TORREITER, Quintino L. TRIANNI
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Patent number: 8659310Abstract: A method and system for performing a self-test of power supply quality for an integrated circuit chip within an electronic system. The electronic system is subjected to a well-defined repetitive activity, such as by using an amplitude modulated system clock tree. With the repetitive activity causing current consumption within the chip, time-domain local power supply voltage (U(t)) is measured for a location on the chip. A set of time-domain measured voltage data (U(t)) is accumulated and transformed into the frequency domain to yield a local voltage profile (U(f)). The local voltage profile (U(f)) is compared with a reference voltage profile (U0(f)) to verify whether power supply quality at the chip location under test is adequate. Alternatively, a local impedance profile Z(f) evaluated from the local voltage profile (U(f)) may be compared to a reference impedance profile Z0(f).Type: GrantFiled: April 15, 2011Date of Patent: February 25, 2014Assignee: International Business Machines CorporationInventors: Martin Eckert, Roland Frech, Jochen Supper, Otto A. Torreiter
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Publication number: 20130343200Abstract: Network power fault detection. At least one first network device is instructed to temporarily disconnect from a power supply path of a network, and at least one characteristic of the power supply path of the network is measured at a second network device connected to the network while the at least one first network device is temporarily disconnected from the network.Type: ApplicationFiled: June 7, 2013Publication date: December 26, 2013Inventors: Martin Eckert, Roland Frech, Claudio Siviero, Jochen Supper, Otto A. Torreiter, Thomas-Michael Winkel