Patents by Inventor Padmapani Nallan

Padmapani Nallan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6440870
    Abstract: The present invention relates to a method of etching tungsten or tungsten nitride in semiconductor structures, and particularly to the etching of gate electrodes which require precise control over the etching process. We have discovered a method of etching tungsten or tungsten nitride which permits precise etch profile control while providing excellent selectivity, of at least 175:1, for example, in favor of etching tungsten or tungsten nitride rather than an adjacent oxide layer. Typically, the oxide is selected from silicon oxide, silicon oxynitride, tantalum pentoxide, zirconium oxide, and combinations thereof. The method appears to be applicable to tungsten or tungsten nitride, whether deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD).
    Type: Grant
    Filed: January 5, 2001
    Date of Patent: August 27, 2002
    Assignee: Applied Materials, Inc.
    Inventors: Padmapani Nallan, Hakeem Oluseyi
  • Patent number: 6423644
    Abstract: The present invention relates to a method of etching tungsten or tungsten nitride in semiconductor structures, and particularly to the etching of gate electrodes which require precise control over the etching process. We have discovered a method of etching tungsten or tungsten nitride which permits precise etch profile control while providing excellent selectivity, of at least 175:1, for example, in favor of etching tungsten or tungsten nitride rather than an adjacent oxide layer. Typically the oxide is selected from silicon oxide, silicon oxynitride, tantalum oxide, zirconium oxide, and combinations thereof. The method appears to be applicable to tungsten or tungsten nitride, whether deposited by physical vapor deposition (PVD) of chemical vapor deposition (CVD).
    Type: Grant
    Filed: July 12, 2000
    Date of Patent: July 23, 2002
    Assignee: Applied Materials, Inc.
    Inventors: Padmapani Nallan, Hakeem Oluseyi
  • Patent number: 6399507
    Abstract: In accordance with the present invention, process parameters are controlled to provide a stable etch plasma. We have discovered that it is possible to operate a stable plasma with a portion of the power deposited to the plasma being a capacitive contribution and a portion of the power deposited being an inductive contribution. In particular, a stable plasma may be obtained within two process regions. In the first region, the gradient of the capacitive power to the power applied to the inductively coupled source for plasma generation [∂Pcap/∂PRF] is greater than 0. In the second region, plasma stability is controlled so that [∂Pcap/∂PRF] is less than 0 and so that Pcap<<PRF. Typically, the magnitude of Pcap is less than about 10% of the magnitude of PRF.
    Type: Grant
    Filed: September 22, 1999
    Date of Patent: June 4, 2002
    Assignee: Applied Materials, Inc.
    Inventors: Padmapani Nallan, John Holland, Valentin Todorov, Thorsten Lill
  • Patent number: 6368978
    Abstract: The present invention is a method for hydrogen-free plasma etching of indium tin oxide using a plasma generated from an etchant gas containing chlorine as a major constituent (i.e., chlorine comprises at least 20 atomic %, preferably at least 50 atomic %, of the etchant gas). Etching is performed at a substrate temperature of 100° C. or lower. The chlorine-comprising gas is preferably Cl2. The etchant gas may further comprise a non-reactive gas, which is used to provide ion bombardment of the surface being etched, and which is preferably argon. The present invention provides a clean, fast method for plasma etching indium tin oxide. The method of the invention is particularly useful for etching a semiconductor device film stack which includes at least one layer of a material that would be adversely affected by exposure to hydrogen, such as N- or P-doped silicon.
    Type: Grant
    Filed: March 4, 1999
    Date of Patent: April 9, 2002
    Assignee: Applied Materials, Inc.
    Inventors: Ajay Kumar, Padmapani Nallan, Jeffrey D. Chinn
  • Publication number: 20020028582
    Abstract: The present invention relates to a method of etching tungsten or tungsten nitride in semiconductor structures, and particularly to the etching of gate electrodes which require precise control over the etching process. We have discovered a method of etching tungsten or tungsten nitride which permits precise etch profile control while providing excellent selectivity, of at least 175:1, for example, in favor of etching tungsten or tungsten nitride rather than an adjacent oxide layer. Typically, the oxide is selected from silicon oxide, silicon oxynitride, tantalum pentoxide, zirconium oxide, and combinations thereof. The method appears to be applicable to tungsten or tungsten nitride, whether deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD).
    Type: Application
    Filed: January 5, 2001
    Publication date: March 7, 2002
    Applicant: Applied Materials, Inc.
    Inventors: Padmapani Nallan, Hakeem Oluseyi
  • Patent number: 6322714
    Abstract: A method of etching a silicon-containing layer 170 on a substrate 45 comprises the steps of placing the substrate 45 on a support 75 in a process chamber 50. The substrate 45 is exposed to an energized process gas comprising a bromine-containing gas, a chlorine-containing gas, an inorganic fluorinated gas, and an oxygen gas. The volumetric flow ratio of the gas constituents is selected so that the energized process gas etches regions 180a,b having different concentrations of dopant in the polysilicon layer 170 at substantially the same etching rate. Optionally, the gas composition is also tailored to simultaneously clean off etch residue from the internal surfaces of a process chamber 50 during etching of the substrate 45.
    Type: Grant
    Filed: July 16, 1998
    Date of Patent: November 27, 2001
    Assignee: Applied Materials Inc.
    Inventors: Padmapani Nallan, Jeffrey Chinn, Stephen Yuen
  • Patent number: 6132631
    Abstract: An etchant mixture of carbon tetrafluoride and argon in a plasma etch chamber produces straight walled isolation trenches in a silicon nitride layer, the trenches having rounded bottoms and no microtrenching.
    Type: Grant
    Filed: August 8, 1997
    Date of Patent: October 17, 2000
    Assignee: Applied Materials, Inc.
    Inventors: Padmapani Nallan, Ajay Kumar, Jeffrey Chinn
  • Patent number: 6069086
    Abstract: An etchant composition for etching straight walled, tapered trenches in silicon comprising chlorine, nitrogen and a mixture of helium and oxygen. The resultant trenches can be readily filled with a dielectric material without the formation of voids. The etchant of the invention is less corrosive, and thus provides increased chamber life and reduced costs over hydrogen bromide-containing etchants.
    Type: Grant
    Filed: April 30, 1998
    Date of Patent: May 30, 2000
    Assignee: Applied Materials, Inc.
    Inventors: Padmapani Nallan, Ganming Zhao, Jeff Chinn, Thalia Kong