Patents by Inventor Pak-Lung Seto

Pak-Lung Seto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7650540
    Abstract: A method according to one embodiment may include communicating, by a far end device with a near end device, using a Serial ATA (SATA) communications protocol; receiving, by the far end device, a SATA signal sequence having two bits, the state of which define at least one loopback mode; defining, by the far end device, a reserved and/or error state if both of the bits are set; and processing, by the far end device, the two bits together to determine if the two bits are in a state that defines at least one loopback mode or if the two bits are set. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.
    Type: Grant
    Filed: July 21, 2006
    Date of Patent: January 19, 2010
    Assignee: Intel Corporation
    Inventors: Luke L. Chang, Pak-Lung Seto, Naichih Chang
  • Patent number: 7643410
    Abstract: A bridge for translating a first storage protocol to a second protocol includes an affiliation manager. The affiliation manager accepts a connection from a host and establishes a connection between a device that uses the second protocol and the host that uses the second protocol. The affiliation manager monitors commands received from the host and responses received from the device on the connection. Upon detecting no pending commands for the device, the bridge may close the connection to the host if there is another host requesting a new connection to the device and establish the new connection between the device and the other host.
    Type: Grant
    Filed: March 29, 2006
    Date of Patent: January 5, 2010
    Assignee: Intel Corporation
    Inventors: Naichih Chang, Pak-Lung Seto
  • Patent number: 7620751
    Abstract: According to one embodiment, a host device is disclosed. The host device includes a logic component to provide an indication of a number of commands issued to a target device, and a task scheduler to schedule commands based on the number of issued commands provided by the logic component.
    Type: Grant
    Filed: September 27, 2005
    Date of Patent: November 17, 2009
    Assignee: Intel Corporation
    Inventors: Nai-Chih Chang, Victor Lau, Pak-lung Seto
  • Publication number: 20090125908
    Abstract: According to one embodiment, an apparatus is disclosed. The apparatus includes a port having a plurality of lanes, a plurality of protocol engines. Each protocol engine is associated with one of the plurality of lanes, and processes tasks to be forwarded to a plurality of remote nodes. The apparatus also includes a first port task scheduler (PTS) to manage the tasks to be forwarded to the one or more of the plurality of protocol engines. The first PTS includes a register to indicate which of the plurality of protocol engines the first PTS is to support.
    Type: Application
    Filed: November 10, 2008
    Publication date: May 14, 2009
    Inventors: Tracey L. Gustafson, Pak-lung Seto, Gary Y. Tsao, Nai-Chih Chang, Victor Lau
  • Publication number: 20090119413
    Abstract: Provided are a method and device for address assignment for adaptor interfaces. An initial configuration is maintained assigning multiple local interfaces to one initial local address. For each local interface, a remote address of a remote interface on at least one remote device to which the local interface connects is received. The initial local address is used to identify the local interfaces assigned to the initial local address in response to receiving a same remote address for each remote interface connected to the local interfaces assigned the initial local address.
    Type: Application
    Filed: January 9, 2009
    Publication date: May 7, 2009
    Inventor: Pak-Lung SETO
  • Patent number: 7516257
    Abstract: According to one embodiment, a system is disclosed. The system includes an initiator device to transmit input/output (I/O) write data and a target device, coupled to the initiator device, to receive the write data from the initiator device as a first segment of data and a second segment of data. The target device re-transmits a transfer ready frame to force the initiator device to retransmit the second segment in response to detecting an uncorrectable error in the second segment.
    Type: Grant
    Filed: September 27, 2005
    Date of Patent: April 7, 2009
    Assignee: Intel Corporation
    Inventors: Victor Lau, Pak-lung Seto, Nai-Chih Chang
  • Patent number: 7506080
    Abstract: A frame based data transfer device includes a receive frame parser, a receive frame processor, and a DMA engine. The receive frame parser receives a frame, stores framing information from the frame in a receive header queue, and stores an information unit from the frame in an information unit buffer. The receive frame processor is coupled to the receive header queue. The receive frame processor reads a transport layer task context as determined by a tag field in the framing information, determines how to handle the frame from the transport layer task context and framing information, generates a DMA descriptor, and stores an updated transport layer task context. The DMA engine is coupled to the information unit buffer and receive frame processor. The DMA engine reads a DMA task context, transfers the information unit to a destination memory by processing the DMA descriptor, and stores an updated DMA task context.
    Type: Grant
    Filed: September 16, 2005
    Date of Patent: March 17, 2009
    Assignee: Inter Corporation
    Inventors: Victor Lau, Pak-lung Seto, Suresh Chemudupati, Naichih Chang, William Halleck
  • Patent number: 7502865
    Abstract: Provided are a method, system, and article of manufacture for assigning addresses for adaptor interfaces. An initial configuration assigning multiple local interfaces to one initial local address is maintained. For each local interface, a remote address of a remote interface on at least one remote device to which the local interface connects is received. The initial local address is used to identify the local interfaces assigned to the initial local address in response to receiving a same remote address for each remote interface connected to the local interfaces assigned the initial local address.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: March 10, 2009
    Assignee: Intel Corporation
    Inventor: Pak-Lung Seto
  • Patent number: 7453904
    Abstract: A method according to one embodiment may include receiving a portion of an inbound frame compliant with a first communication protocol, translating the portion of the inbound frame into a translated portion compliant with a second communication protocol; and constructing an outbound frame comprising the translated portion before an entirety of the inbound frame is received. A cut-through communication protocol translation bridge may comprise an integrated circuit capable of performing such a method. Of course, many alternatives, variations, and modifications are possible without departing from these embodiments.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: November 18, 2008
    Assignee: Intel Corporation
    Inventor: Pak-Lung Seto
  • Patent number: 7451255
    Abstract: According to one embodiment, an apparatus is disclosed. The apparatus includes a port having a plurality of lanes, a plurality of protocol engines. Each protocol engine is associated with one of the plurality of lanes, and processes tasks to be forwarded to a plurality of remote nodes. The apparatus also includes a first port task scheduler (PTS) to manage the tasks to be forwarded to the one or more of the plurality of protocol engines. The first PTS includes a register to indicate which of the plurality of protocol engines the first PTS is to support.
    Type: Grant
    Filed: September 28, 2005
    Date of Patent: November 11, 2008
    Assignee: Intel Corporation
    Inventors: Tracey Gustafson, Pak-lung Seto, Gary Y. Tsao, Nai-Chih Chang, Victor Lau
  • Patent number: 7450588
    Abstract: According to one embodiment, a system is disclosed. The system includes an input/output (IO) frame manager (IOFM) to route received IO frames to one or more IO lists and one or more IO frame order managers (IOFOMs) to reorder frames received for each IO list according to a relative order.
    Type: Grant
    Filed: August 24, 2006
    Date of Patent: November 11, 2008
    Assignee: Intel Corporation
    Inventors: Nai-Chih Chang, Pak-lung Seto
  • Patent number: 7447826
    Abstract: A method according to one embodiment may include receiving data in a receive buffer, the receive buffer comprising a plurality of buffers, and sending a hold command to a transmitting node currently sending data to hold transmission of additional data when a level of the data in the receive buffer reaches a high threshold level. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: November 4, 2008
    Assignee: Intel Corporation
    Inventors: Pak-Lung Seto, Richard C. Beckett, Devicharan Devidas
  • Patent number: 7415549
    Abstract: According to one embodiment, a storage device is disclosed. The storage device includes a port having one or more lanes and a direct memory access (DMA) Descriptor Manager (DM). The DM generates and tracks completion of descriptors. The DM includes a first completion lookup table to track one or more fields of an input/output (I/O) context received at a first lane.
    Type: Grant
    Filed: September 27, 2005
    Date of Patent: August 19, 2008
    Assignee: Intel Corporation
    Inventors: Kiran Vemula, Victor Lau, Pak-lung Seto, Nai-Chih Chang, William Halleck, Suresh Chemudupati, Ankit Parikh, Gary Y. Tsao
  • Patent number: 7412540
    Abstract: A method according to one embodiment may include transmitting a frame from a transmitting device to a receiving device via a communication network of a data storage system, enabling an encoding operation of the transmitting device to encode decoded data into encoded data and transmitting the encoded data in the frame via the communication network if the receiving device has a decoding operation capable of decoding the encoded data into the decoded data, and disabling the encoding operation and transmitting the decoded data in the frame via the communication network to the receiving device if the receiving device does not have the decoding operation capable of decoding the encoded data into the decoded data. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: August 12, 2008
    Assignee: Intel Corporation
    Inventors: Pak-Lung Seto, Deif N. Atallah
  • Publication number: 20080183921
    Abstract: A method and apparatus improves a link rate to a plurality of storage devices accessible through a port multiplier. An SATA/STP Transport Layer Transmit Processor in a FIS-based switching Port Multiplier system may service a next task to be transmitted to a next device accessible through the port multiplier even if the current task to a current device is stalled.
    Type: Application
    Filed: January 29, 2007
    Publication date: July 31, 2008
    Inventors: Naichih Chang, Pak-Lung Seto
  • Publication number: 20080126608
    Abstract: According to one embodiment, a system is disclosed. The system includes an input/output (IO) frame manager (IOFM) to route received IO frames to one or more IO lists and one or more IO frame order managers (IOFOMs) to reorder frames received for each IO list according to a relative order.
    Type: Application
    Filed: August 24, 2006
    Publication date: May 29, 2008
    Inventors: Nai-Chih Chang, Pak-lung Seto
  • Publication number: 20080126623
    Abstract: An apparatus and method is provided to facilitate Input/Output (I/O) transfer in resource limited storage environment. Scatter gather list, segment and memory data buffer allocation are dynamically managed. I/O transfer performance is increased through the use of a data cut-through buffer mechanism.
    Type: Application
    Filed: June 23, 2006
    Publication date: May 29, 2008
    Inventors: Naichih Chang, Pak-Lung Seto, Victor Lau
  • Patent number: 7376147
    Abstract: Provided are a method, adaptor, system, and program for receiving a transmission at one of multiple connections. Information is maintained on storage interconnect architectures and transmission characteristics, wherein the storage interconnect architectures have different transmission characteristics. At least one transmission characteristic of the received transmission is determined and a determination is made from the information of the storage interconnect architecture associated with the determined transmission characteristic. The information on the determined storage interconnect architecture is used to process the transmission and determine a transport layer for the received transmission, wherein there is one transport layer for each supported transport protocol. The transmission is forwarded to the determined transport layer.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: May 20, 2008
    Assignee: Intel Corporation
    Inventors: Pak-Lung Seto, Deif N. Atallah
  • Patent number: 7376789
    Abstract: Apparatus, systems, methods, and articles may operate to restrict an order of processing of frames associated with a task context stored in at least one context cache memory location. The order of processing may be restricted by selectively locking the context for exclusive use by a selected lane in a multi-lane serial-attached small computer system interface (SAS) hardware protocol engine while the selected lane processes a selected one of the frames.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: May 20, 2008
    Assignee: Intel Corporation
    Inventors: William Halleck, Pak-lung Seto, Victor Lau
  • Patent number: 7373443
    Abstract: Provided is a method for interfacing with storage units, including a backplane, at least one slot in the storage enclosure for receiving one storage unit, and two physical interfaces on the backplane for at least one slot. The storage unit is capable of being positioned in the slot to mate with one of the two physical interfaces for the slot, wherein each physical interface supports different storage interconnect architectures.
    Type: Grant
    Filed: October 19, 2006
    Date of Patent: May 13, 2008
    Assignee: Intel Corporation
    Inventor: Pak-Lung Seto