Patents by Inventor Pak-Lung Seto

Pak-Lung Seto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7373442
    Abstract: Provided is a system for interfacing with storage units, including a backplane, at least one slot in the storage enclosure for receiving one storage unit, and two physical interfaces on the backplane for at least one slot. The storage unit is capable of being positioned in the slot to mate with one of the two physical interfaces for the slot, wherein each physical interface supports different storage interconnect architectures.
    Type: Grant
    Filed: October 19, 2006
    Date of Patent: May 13, 2008
    Assignee: Intel Corporation
    Inventor: Pak-Lung Seto
  • Publication number: 20080104264
    Abstract: Link level load balancing is provided based on time utilization of a link or workload utilization of a device. Time utilization achieves load balancing by giving each device the same amount of connection time to perform Input/Output tasks. Workload utilization achieves load balancing by managing a number of frames or bytes transmitted to each device.
    Type: Application
    Filed: November 1, 2006
    Publication date: May 1, 2008
    Inventors: Vicky P. Duerk, Pak-Lung Seto
  • Patent number: 7366802
    Abstract: A method according to one embodiment may include reserving a plurality of buffers having an aggregate capacity, receiving a frame having a size less than the aggregate capacity, and releasing at least one of the plurality of buffers that is unused to store the frame. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: April 29, 2008
    Assignee: Intel Corporation
    Inventor: Pak-Lung Seto
  • Patent number: 7366817
    Abstract: Apparatus and systems, as well as methods and articles, may bridge between a link layer and a transport layer in a multi-lane serial-attached small computer system interface (SCSI)-serial SCSI protocol (SAS-SSP) device. A lane number first-in first-out buffer (FIFO) array may operate to order frame processing such that frames associated with an input-output (IO) stream subset of a plurality of SAS-SSP frames received at a plurality of lane receive buffers are processed in an IO stream subset order.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: April 29, 2008
    Assignee: Intel Corporation
    Inventors: Nai-chih Chang, Pak-lung Seto, Victor Lau
  • Patent number: 7363395
    Abstract: A method according to one embodiment may include determining, at least in part, by an intermediate device at least one communication protocol via which at least one storage device connected to the intermediate device is capable of communicating. In this embodiment, the intermediate device may be capable of controlling, at least in part, by the intermediate device, at least one data stream coming from the at least one storage device in accordance with at least one communication protocol. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: April 22, 2008
    Assignee: Intel Corporation
    Inventor: Pak-Lung Seto
  • Patent number: 7353302
    Abstract: In one embodiment, an apparatus may include a plurality of ports capable of being coupled to a plurality of devices via an associated plurality of communication links, the links being compliant with Serial Attached Small Computer Systems Interface (SAS) protocol. The apparatus may further include circuitry to provide selectable communication control between at least a first device and at least a second device of the plurality of devices. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: April 1, 2008
    Assignee: Intel Corporation
    Inventor: Pak-Lung Seto
  • Publication number: 20080056424
    Abstract: A noise filtering system provides adaptive noise filtering in the physical layer of serial and parallel interfaces for storage protocol applications. The system provides adaptive noise filtering for both hot plug and hot removal applications.
    Type: Application
    Filed: September 1, 2006
    Publication date: March 6, 2008
    Inventors: Naichih Chang, Pak-Lung Seto, Luke L. Chang
  • Publication number: 20080019280
    Abstract: A method according to one embodiment may include communicating, by a far end device with a near end device, using a Serial ATA (SATA) communications protocol; receiving, by the far end device, a SATA signal sequence having two bits, the state of which define at least one loopback mode; defining, by the far end device, a reserved and/or error state if both of the bits are set; and processing, by the far end device, the two bits together to determine if the two bits are in a state that defines at least one loopback mode or if the two bits are set. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.
    Type: Application
    Filed: July 21, 2006
    Publication date: January 24, 2008
    Inventors: Luke L. Chang, Pak-Lung Seto, Naichih Chang
  • Publication number: 20070299999
    Abstract: A state machine encoded in state machine instructions is stored in non-volatile memory, and loaded into volatile memory in a hardware engine for use by the hardware engine upon power up or reset. Storing the state machine for a phy reset sequence in non-volatile memory coupled to the hardware engine allows protocol modifications to the state machine to be performed in the non-volatile memory.
    Type: Application
    Filed: June 21, 2006
    Publication date: December 27, 2007
    Inventors: Vicky Duerk, Pak-Lung Seto
  • Publication number: 20070237174
    Abstract: A bridge for translating a first storage protocol to a second protocol includes an affiliation manager. The affiliation manager accepts a connection from a host and establishes a connection between a device that uses the second protocol and the host that uses the second protocol. The affiliation manager monitors commands received from the host and responses received from the device on the connection. Upon detecting no pending commands for the device, the bridge may close the connection to the host if there is another host requesting a new connection to the device and establish the new connection between the device and the other host.
    Type: Application
    Filed: March 29, 2006
    Publication date: October 11, 2007
    Inventors: Naichih Chang, Pak-Lung Seto
  • Publication number: 20070233916
    Abstract: Provided is a method for interfacing with storage units, including a backplane, at least one slot in the storage enclosure for receiving one storage unit, and two physical interfaces on the backplane for at least one slot. The storage unit is capable of being positioned in the slot to mate with one of the two physical interfaces for the slot, wherein each physical interface supports different storage interconnect architectures.
    Type: Application
    Filed: October 19, 2006
    Publication date: October 4, 2007
    Inventor: Pak-Lung Seto
  • Patent number: 7272745
    Abstract: A method according to one embodiment may include assigning a tag to at least one transactions in which at least one data frame is at least one of transmitted or received by at least one functional block. The method may also include discovering, by a functional block, if an error occurs in at least one data frame. The method may also include associating the error with the tag and generating a flush command to at least one functional block to flush data frames associated with said tag. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: September 18, 2007
    Assignee: Intel Corporation
    Inventor: Pak-Lung Seto
  • Publication number: 20070198761
    Abstract: A host device is disclosed. The host device includes a receive frame and primitive sequence processor, a transmitter and a connection manager to open and terminate a connection with a target device.
    Type: Application
    Filed: December 28, 2005
    Publication date: August 23, 2007
    Inventors: Vicky Duerk, Pak-lung Seto
  • Publication number: 20070150683
    Abstract: A method, computer program product, system (including a circuit card), and integrated circuit for initializing a buffer pool, such that the buffer pool includes a plurality of data buffers available for use during a plurality of I/O transfers. In response to the initiation of a first I/O transfer concerning a first data portion being transferred from a first data source to a first data target, the first data portion is written to a first portion of the plurality of data buffers. The first data portion is transferred to the first data target, and the first portion of the plurality of data buffers is released back to the buffer pool for use during one or more subsequent I/O transfers.
    Type: Application
    Filed: December 28, 2005
    Publication date: June 28, 2007
    Inventors: Naichih Chang, Pak-Lung Seto, Victor Lau
  • Publication number: 20070147522
    Abstract: An apparatus according to one embodiment may include an integrated circuit. The integrated circuit may include a plurality communication channels. The integrated circuit may be is capable of communicating with at least one remote node external to the integrated circuit, via at least one of the communication channels, in accordance with at least one communication protocol. Each of said plurality of communication channels may provide a communication path between a host system and at least one remote node. The integrated circuit may be further capable of operating each communication channel independently of each other and independently of the host system. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.
    Type: Application
    Filed: December 28, 2005
    Publication date: June 28, 2007
    Inventors: Pak-Lung Seto, Gary Tsao
  • Patent number: 7231581
    Abstract: A method according to one embodiment may include: at least one of transmitting and receiving a first portion of a first protected data block within a first frame; and at least one of transmitting and receiving a second portion of the first protected data block within a second frame. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: June 12, 2007
    Assignee: Intel Corporation
    Inventor: Pak-Lung Seto
  • Publication number: 20070118835
    Abstract: A method and apparatus for managing task context is provided. Upon initialization, a protocol engine provides context resources available for processing tasks to a task issuer. Based on available context resources, the task issuer creates and manages a free list of available task context indices and assigns an index to a task prior to storing task context in a context memory accessible to both the task issuer and the protocol engine and issuing the task to the protocol engine.
    Type: Application
    Filed: November 22, 2005
    Publication date: May 24, 2007
    Inventors: William Halleck, Victor Lau, Pak-Lung Seto, Naichih Chang
  • Patent number: 7221531
    Abstract: According to one embodiment, a system is disclosed. The system includes one or more storage devices, a host bus adapter (HBA) and a bridging device coupled between the one or more storage device and the HBA. The bridging device includes a register having bits corresponding to each of the one or more storage devices. Each bit indicates whether staggered spin-up is enabled at a corresponding storage device.
    Type: Grant
    Filed: September 12, 2005
    Date of Patent: May 22, 2007
    Assignee: Intel Corporation
    Inventors: Vicky P. Duerk, Nai-Chih Chang, Pak-lung Seto, Victor Lau
  • Publication number: 20070088860
    Abstract: According to one embodiment, a host device is disclosed. The host device includes a logic component to provide an indication of a number of commands issued to a target device, and a task scheduler to schedule commands based on the number of issued commands provided by the logic component.
    Type: Application
    Filed: September 27, 2005
    Publication date: April 19, 2007
    Inventors: Nai-Chih Chang, Victor Lau, Pak-lung Seto
  • Publication number: 20070088895
    Abstract: According to one embodiment, an apparatus is disclosed. The apparatus includes a port having a plurality of lanes, a plurality of protocol engines. Each protocol engine is associated with one of the plurality of lanes, and processes tasks to be forwarded to a plurality of remote nodes. The apparatus also includes a first port task scheduler (PTS) to manage the tasks to be forwarded to the one or more of the plurality of protocol engines. The first PTS includes a register to indicate which of the plurality of protocol engines the first PTS is to support.
    Type: Application
    Filed: September 28, 2005
    Publication date: April 19, 2007
    Inventors: Tracey Gustafson, Pak-lung Seto, Gary Tsao, Nai-Chih Chang, Victor Lau