Abstract: A device includes a semiconductive fin, an isolation structure, a gate structure, dielectric spacers, and source/drain epitaxial structures. The isolation structure surrounds a bottom portion of the semiconductive fin. The gate structure is over the semiconductive fin. The dielectric spacers are on opposite sides of the semiconductive fin and over the isolation structure. The dielectric spacers include nitride. The source/drain epitaxial structures are on opposite sides of the gate structure and over the dielectric spacers. The source/drain epitaxial structures have hexagon shapes.

Abstract: The present disclosure describes a semiconductor device having facet-free epitaxial structures with a substantially uniform thickness. The semiconductor device includes a fin structure on a substrate. The fin structure includes a fin bottom portion and a fin top portion. A top surface of the fin bottom portion is wider than a bottom surface of the fin top portion. The semiconductor device further includes a dielectric layer on the fin top portion, an amorphous layer on the dielectric layer, and an epitaxial layer. The epitaxial layer is on a top surface of the amorphous layer, sidewall surfaces of the amorphous layer, the dielectric layer, the fin top portion, and the top surface of the fin bottom portion.

Abstract: A method of forming a semiconductor device includes providing a substrate having a recess, and growing an epitaxial feature in the recess. The method of growing the epitaxial feature includes: (a) growing a sub-layer of the epitaxial feature; (b) selectively etching the sub-layer of the epitaxial feature while providing a first UV radiation; and (c) repeating step (a) and step (b) alternately multiple times.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes multiple semiconductor nanostructures, and the semiconductor nanostructures include a first semiconductor material. The semiconductor device structure also includes multiple epitaxial structures extending from edges of the semiconductor nanostructures. The epitaxial structures include a second semiconductor material that is different than the first semiconductor material. The semiconductor device structure further includes a gate stack wrapped around the semiconductor nanostructures.

Abstract: The present disclosure provides channel structures of a semiconductor device and fabricating methods thereof. The method can include forming a superlattice structure with first nanostructured layers and second nanostructured layers on a fin structure. The method can also include removing the second nanostructured layers to form multiple gate openings; forming a germanium epitaxial growth layer on the first nanostructured layers at a first temperature and a first pressure; and increasing the first temperature to a second temperature and increasing the first pressure to a second pressure over a first predetermined period of time. The method can further include annealing the germanium epitaxial growth layer at the second temperature and the second pressure in the chamber over a second predetermined period of time to form a cladding layer surrounding the first nanostructured layers.

Abstract: The present disclosure describes a semiconductor device having facet-free epitaxial structures with a substantially uniform thickness. The semiconductor device includes a fin structure on a substrate. The fin structure includes a fin bottom portion and a fin top portion. A top surface of the fin bottom portion is wider than a bottom surface of the fin top portion. The semiconductor device further includes a dielectric layer on the fin top portion, an amorphous layer on the dielectric layer, and an epitaxial layer. The epitaxial layer is on a top surface of the amorphous layer, sidewall surfaces of the amorphous layer, the dielectric layer, the fin top portion, and the top surface of the fin bottom portion.

Abstract: A semiconductor device and a method of forming the same are provided. A method includes forming a gate over a semiconductor structure. An epitaxial source/drain region is formed adjacent the gate. A dielectric layer is formed over the epitaxial source/drain region. An opening extending through the dielectric layer and exposing the epitaxial source/drain region is formed. A conductive material is non-conformally deposited in the opening. The conductive material fills the opening in a bottom-up manner.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first semiconductor nanostructure and a second semiconductor nanostructure stacked over a substrate. The semiconductor device structure also includes a first epitaxial structure connecting the first semiconductor nanostructure and a second epitaxial structure connecting the second semiconductor nanostructure. The semiconductor device structure further includes a gate stack wrapped around the first semiconductor nanostructure and the second semiconductor nanostructure. In addition, the semiconductor device structure includes a conductive contact electrically connected to the epitaxial structures. The conductive contact has a portion extending towards the gate stack from terminals of the first epitaxial structure and the second epitaxial structures. The first epitaxial structure is wider than the portion of the conductive contact.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method of forming a semiconductor device comprises forming a fin over a substrate, wherein the fin comprises a first semiconductor layer and a second semiconductor layer comprising different semiconductor materials, and the fin includes a channel region and a source/drain region; forming a dummy gate structure over the substrate and the fin; etching a portion of the fin in the source/drain region; selectively removing an edge portion of the second semiconductor layer in the channel region of the fin such that the second semiconductor layer is recessed, and an edge portion of the first semiconductor layer is suspended; performing a reflow process to the first semiconductor layer to form an inner spacer, wherein the inner spacer forms sidewall surfaces of the source/drain region of the fin; and epitaxially growing a sour/drain feature in the source/drain region.

Abstract: A method of fabricating a semiconductor device with superlattice structures on a substrate with an embedded isolation structure is disclosed. The method includes forming an etch stop layer on a substrate, forming a superlattice structure on the etch stop layer, depositing an isolation layer on the superlattice structure, depositing a semiconductor layer on the isolation layer, forming a bi-layer isolation structure on the semiconductor layer, removing the substrate and the etch stop layer, etching the superlattice structure, the isolation layer, the semiconductor layer, and the bi-layer isolation structure to form a fin structure, and forming a gate-all-around structure on the fin structure.

Abstract: The present disclosure provides channel structures of a semiconductor device and fabricating methods thereof. The method can include forming a superlattice structure with first nanostructured layers and second nanostructured layers on a fin structure. The method can also include removing the second nanostructured layers to form multiple gate openings; forming a germanium epitaxial growth layer on the first nanostructured layers at a first temperature and a first pressure; and increasing the first temperature to a second temperature and increasing the first pressure to a second pressure over a first predetermined period of time. The method can further include annealing the germanium epitaxial growth layer at the second temperature and the second pressure in the chamber over a second predetermined period of time to form a cladding layer surrounding the first nanostructured layers.

Abstract: A method of fabricating a semiconductor device with superlattice structures on a substrate with an embedded isolation structure is disclosed. The method includes forming an etch stop layer on a substrate, forming a superlattice structure on the etch stop layer, depositing an isolation layer on the superlattice structure, depositing a semiconductor layer on the isolation layer, forming a bi-layer isolation structure on the semiconductor layer, removing the substrate and the etch stop layer, etching the superlattice structure, the isolation layer, the semiconductor layer, and the bi-layer isolation structure to form a fin structure, and forming a gate-all-around structure on the fin structure.

Abstract: A first dielectric layer is selectively formed such that the first dielectric layer is formed over a source/drain region of a first type of transistor but not over a source/drain region of a second type of transistor. The first type of transistor and the second type of transistor have different types of conductivity. A first silicide layer is selectively formed such that the first silicide layer is formed over the source/drain region of the second type of transistor but not over the source/drain region of the first type of transistor. The first dielectric layer is removed. A second silicide layer is formed over the source/drain region of the first type of transistor.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate and a semiconductor layer formed over the substrate. The semiconductor device further includes a first channel layer and a second channel layer and a first insulating structure interposing the first channel layer and the semiconductor layer and a second insulating structure interposing the first channel layer and the second channel layer. The semiconductor device further includes a gate stack abutting the first channel layer and the second channel layer, and the gate stack includes a first portion vertically sandwiched between the first channel layer and the semiconductor layer and a second portion vertically sandwiched between the first channel layer and the second channel layer.

Abstract: A semiconductor device and a method of forming the same are provided. A method includes forming a gate over a semiconductor structure. An epitaxial source/drain region is formed adjacent the gate. A dielectric layer is formed over the epitaxial source/drain region. An opening extending through the dielectric layer and exposing the epitaxial source/drain region is formed. A conductive material is non-conformally deposited in the opening. The conductive material fills the opening in a bottom-up manner.

Abstract: A first dielectric layer is selectively formed such that the first dielectric layer is formed over a source/drain region of a first type of transistor but not over a source/drain region of a second type of transistor. The first type of transistor and the second type of transistor have different types of conductivity. A first silicide layer is selectively formed such that the first silicide layer is formed over the source/drain region of the second type of transistor but not over the source/drain region of the first type of transistor. The first dielectric layer is removed. A second silicide layer is formed over the source/drain region of the first type of transistor.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method of forming a semiconductor device comprises forming a fin over a substrate, wherein the fin comprises a first semiconductor layer and a second semiconductor layer comprising different semiconductor materials, and the fin includes a channel region and a source/drain region; forming a dummy gate structure over the substrate and the fin; etching a portion of the fin in the source/drain region; selectively removing an edge portion of the second semiconductor layer in the channel region of the fin such that the second semiconductor layer is recessed, and an edge portion of the first semiconductor layer is suspended; performing a reflow process to the first semiconductor layer to form an inner spacer, wherein the inner spacer forms sidewall surfaces of the source/drain region of the fin; and epitaxially growing a sour/drain feature in the source/drain region.

Abstract: A method includes etching a hybrid substrate to form a recess in the hybrid substrate, in which the hybrid substrate includes a first semiconductor layer, a dielectric layer over the first semiconductor layer, and a second semiconductor layer over the first semiconductor layer, in which after the etching, a top surface of the first semiconductor layer is exposed to the recess; forming a spacer on a sidewall of the recess, in which the spacer is slanted at a first angle relative to a top surface of the first semiconductor layer; reshaping the spacer such that the a first sidewall of the reshaped spacer is slanted at a second angle relative to the top surface of the first semiconductor layer, in which the second angle is greater than the first angle; and performing a first epitaxy process to grow an epitaxy semiconductor layer in the recess after reshaping the spacer.

Abstract: A semiconductor device structure according to the present disclosure includes a source feature and a drain feature, at least one channel structure extending between the source feature and the drain feature, a gate structure wrapped around each of the at least one channel structure, a semiconductor layer over the gate structure, a dielectric layer over the semiconductor layer, a doped semiconductor feature extending through the semiconductor layer and the dielectric layer to be in contact with the source feature, a metal contact plug over the doped semiconductor feature, and a buried power rail disposed over the metal contact plug.

Abstract: A semiconductor device includes a substrate, a first semiconductor fin and a gate stack. The first semiconductor fin is over the substrate and includes a first germanium-containing layer and a second germanium-containing layer over the first germanium-containing layer. The first germanium-containing layer has a germanium atomic percentage higher than a germanium atomic percentage of the second germanium-containing layer. The gate stack is across the first semiconductor fin.