Patents by Inventor Pang-Yen Tsai

Pang-Yen Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210098499
    Abstract: A semiconductor device includes a substrate, a first semiconductor fin and a gate stack. The first semiconductor fin is over the substrate and includes a first germanium-containing layer and a second germanium-containing layer over the first germanium-containing layer. The first germanium-containing layer has a germanium atomic percentage higher than a germanium atomic percentage of the second germanium-containing layer. The gate stack is across the first semiconductor fin.
    Type: Application
    Filed: December 11, 2020
    Publication date: April 1, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsung-Yu HUNG, Pei-Wei LEE, Pang-Yen TSAI
  • Publication number: 20210083115
    Abstract: A method of manufacturing a semiconductor device includes forming a first gate stack over a substrate. The method further includes etching the substrate to define a cavity. The method further includes growing a first epitaxial (epi) material in the cavity, wherein the first epi material includes a first upper surface having a first crystal plane. The method further includes growing a second epi material on the first epi material, wherein the second epi material includes a second upper surface having the first crystal plane. The method further includes treating the second epi material, wherein treating the second epi material comprises causing the second upper surface to transform to a second crystal plane different from the first crystal plane.
    Type: Application
    Filed: November 4, 2020
    Publication date: March 18, 2021
    Inventors: Lilly SU, Chii-Horng LI, Ming-Hua YU, Pang-Yen TSAI, Tze-Liang LEE, Yen-Ru LEE
  • Publication number: 20210082773
    Abstract: A method includes etching a hybrid substrate to form a recess in the hybrid substrate, in which the hybrid substrate includes a first semiconductor layer, a dielectric layer over the first semiconductor layer, and a second semiconductor layer over the first semiconductor layer, in which after the etching, a top surface of the first semiconductor layer is exposed to the recess; forming a spacer on a sidewall of the recess, in which the spacer is slanted at a first angle relative to a top surface of the first semiconductor layer; reshaping the spacer such that the a first sidewall of the reshaped spacer is slanted at a second angle relative to the top surface of the first semiconductor layer, in which the second angle is greater than the first angle; and performing a first epitaxy process to grow an epitaxy semiconductor layer in the recess after reshaping the spacer.
    Type: Application
    Filed: November 13, 2020
    Publication date: March 18, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pei-Wei Lee, Tsung-Yu Hung, Pang-Yen Tsai, Yasutoshi Okuno
  • Patent number: 10937876
    Abstract: Examples of an integrated circuit with an interface between a source/drain feature and a contact and examples of a method for forming the integrated circuit are provided herein. In some examples, a substrate is received having a source/drain feature disposed on the substrate. The source/drain feature includes a first semiconductor element and a second semiconductor element. The first semiconductor element of the source/drain feature is oxidized to produce an oxide of the first semiconductor element on the source/drain feature and a region of the source/drain feature with a greater concentration of the second semiconductor element than a remainder of the source/drain feature. The oxide of the first semiconductor element is removed, and a contact is formed that is electrically coupled to the source/drain feature. In some such embodiments, the first semiconductor element includes silicon and the second semiconductor element includes germanium.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: March 2, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ding-Kang Shih, Sung-Li Wang, Pang-Yen Tsai
  • Patent number: 10930755
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method of forming a semiconductor device comprises forming a fin over a substrate, wherein the fin comprises a first semiconductor layer and a second semiconductor layer comprising different semiconductor materials, and the fin includes a channel region and a source/drain region; forming a dummy gate structure over the substrate and the fin; etching a portion of the fin in the source/drain region; selectively removing an edge portion of the second semiconductor layer in the channel region of the fin such that the second semiconductor layer is recessed, and an edge portion of the first semiconductor layer is suspended; performing a reflow process to the first semiconductor layer to form an inner spacer, wherein the inner spacer forms sidewall surfaces of the source/drain region of the fin; and epitaxially growing a sour/drain feature in the source/drain region.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: February 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsungyu Hung, Pang-Yen Tsai, Pei-Wei Lee
  • Publication number: 20210043454
    Abstract: A semiconductor device includes a substrate and a semiconductor layer. The substrate includes a planar portion and a plurality of pillars on a periphery of the planar portion. The pillars are shaped as rectangular columns, and corners of two of the pillars at the same side of the planar portion are aligned in a horizontal direction or a direction perpendicular to the horizontal direction. The semiconductor layer is disposed over the planar portion and between the pillars.
    Type: Application
    Filed: October 13, 2020
    Publication date: February 11, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Wei Lee, Pang-Yen Tsai, Tsung-Yu Hung
  • Publication number: 20210020522
    Abstract: A semiconductor device and a method of making the same are provided. A method according to the present disclosure includes providing a workpiece comprising a first source/drain region in a first device region and a second source/drain region in a second device region, depositing a dielectric layer over the first source/drain region and the second source drain region, forming a first via opening in the dielectric layer to expose the first source/drain region and a second via opening in the dielectric layer to expose the second source/drain region, annealing the workpiece to form a first semiconductor oxide feature over the exposed first source/drain region and a second semiconductor oxide feature over the exposed second source/drain region, removing the first semiconductor oxide feature to expose the first source/drain region in the first via opening in dielectric layer, and selectively forming a first epitaxial feature over the exposed first source/drain region.
    Type: Application
    Filed: July 16, 2019
    Publication date: January 21, 2021
    Inventors: Ding-Kang Shih, Cheng-Long Chen, Pang-Yen Tsai
  • Patent number: 10886270
    Abstract: A method for forming a semiconductor device is provided. The method includes removing a first portion of a substrate to form a recess in the substrate. The method includes forming an epitaxy layer in the recess. The epitaxy layer and the substrate are made of different semiconductor materials. The method includes forming a stacked structure of a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked over the substrate and the epitaxy layer. The method includes removing a second portion of the stacked structure and a third portion of the epitaxy layer to form trenches passing through the stacked structure and extending into the epitaxy layer. The stacked structure is divided into a first fin element and a second fin element by the trenches, and the first fin element and the second fin element are over the substrate and the epitaxy layer respectively.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: January 5, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Winnie Victoria Wei-Ning Chen, Meng-Hsuan Hsiao, Tung-Ying Lee, Pang-Yen Tsai, Yasutoshi Okuno
  • Patent number: 10879131
    Abstract: The present disclosure provides a method for method for forming a semiconductor structure, including providing a substrate with a first well region of a first conductivity type, forming a silicon layer over the first well region, forming a first silicon fin over the first well region, and applying a silicon-free gas source upon the first silicon fin.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tsungyu Hung, Pei-Wei Lee, Pang-Yen Tsai
  • Patent number: 10872906
    Abstract: A semiconductor device includes a substrate, a first semiconductor fin and a gate stack. The first semiconductor fin is over the substrate and includes a first germanium-containing layer and a second germanium-containing layer over the first germanium-containing layer. The first germanium-containing layer has a germanium atomic percentage higher than a germanium atomic percentage of the second germanium-containing layer. The gate stack is across the first semiconductor fin.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: December 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tsung-Yu Hung, Pei-Wei Lee, Pang-Yen Tsai
  • Patent number: 10868009
    Abstract: A method for forming a semiconductor device is provided. The method includes forming a first recess in a substrate. The method includes forming a first semiconductor layer into the first recess. The first semiconductor layer and the substrate are made of different materials, and a first top surface of the first semiconductor layer is lower than a second top surface of the substrate. The method includes forming a second semiconductor layer over the first top surface and the second top surface, wherein a third top surface of the second semiconductor layer over the first top surface is substantially level with the second top surface of the substrate, and the second semiconductor layer and the substrate are made of different materials. The method includes forming a third semiconductor layer over the second semiconductor layer. The third semiconductor layer and the second semiconductor layer are made of different materials.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Winnie Victoria Wei-Ning Chen, Meng-Hsuan Hsiao, Tung-Ying Lee, Pang-Yen Tsai, Yasutoshi Okuno
  • Patent number: 10854748
    Abstract: A semiconductor device includes a first gate stack over a substrate. The semiconductor device further includes a first epitaxial (epi) material in the substrate on a first side of the first gate stack. The first epi material includes a first upper surface having a first crystal plane. The semiconductor device further includes a second epi material in the substrate on a second side of the first gate stack opposite the first side. The second epi material includes a second upper surface having a second crystal plane, and the first crystal plane is different from the second crystal plane.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: December 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Lilly SU, Pang-Yen Tsai, Tze-Liang Lee, Chii-Horng Li, Yen-Ru Lee, Ming-Hua Yu
  • Patent number: 10847413
    Abstract: A semiconductor device and a method of forming the same are provided. A method includes forming a gate over a semiconductor structure. An epitaxial source/drain region is formed adjacent the gate. A dielectric layer is formed over the epitaxial source/drain region. An opening extending through the dielectric layer and exposing the epitaxial source/drain region is formed. A conductive material is non-conformally deposited in the opening. The conductive material fills the opening in a bottom-up manner.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: November 24, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mrunal A Khaderbad, Yasutoshi Okuno, Sung-Li Wang, Pang-Yen Tsai, Shen-Nan Lee, Teng-Chun Tsai
  • Patent number: 10840152
    Abstract: A method includes etching a hybrid substrate to form a recess in the hybrid substrate, in which the hybrid substrate includes a first semiconductor layer, a dielectric layer over the first semiconductor layer, and a second semiconductor layer over the first semiconductor layer, in which after the etching, a top surface of the first semiconductor layer is exposed to the recess; forming a spacer on a sidewall of the recess, in which the spacer is slanted at a first angle relative to a top surface of the first semiconductor layer; reshaping the spacer such that the a first sidewall of the reshaped spacer is slanted at a second angle relative to the top surface of the first semiconductor layer, in which the second angle is greater than the first angle; and performing a first epitaxy process to grow an epitaxy semiconductor layer in the recess after reshaping the spacer.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: November 17, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Pei-Wei Lee, Tsung-Yu Hung, Pang-Yen Tsai, Yasutoshi Okuno
  • Publication number: 20200350314
    Abstract: A semiconductor device includes first and second epitaxial structures, first and second top metal alloy layers, and first and second bottom metal alloy layers. The first and second epitaxial structures have different cross sections. The first and second top metal alloy layers are respectively in contact with the first and second epitaxial structures. The first and second bottom metal alloy layers are respectively in contact with the first and second epitaxial structures and respectively under the first and second top metal alloy layers. The first top metal alloy layer and the first bottom metal alloy layer are made of different materials.
    Type: Application
    Filed: July 13, 2020
    Publication date: November 5, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sung-Li WANG, Pang-Yen TSAI, Yasutoshi OKUNO
  • Patent number: 10811255
    Abstract: Methods of forming semiconductor devices are provided. One of the methods includes following steps. A plurality of hard mask patterns is formed around a region of a substrate, wherein an imaginary connecting line is formed between corners of two of the plurality of hard mask patterns at the same side of the region, and the imaginary connecting line is substantially parallel to or perpendicular to a horizontal direction. A semiconductor layer is formed on the substrate by a selective epitaxial growth process.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: October 20, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Wei Lee, Pang-Yen Tsai, Tsung-Yu Hung
  • Publication number: 20200321336
    Abstract: A method for forming a semiconductor device is provided. The method includes removing a first portion of a substrate to form a recess in the substrate. The method includes forming an epitaxy layer in the recess. The epitaxy layer and the substrate are made of different semiconductor materials. The method includes forming a stacked structure of a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked over the substrate and the epitaxy layer. The method includes removing a second portion of the stacked structure and a third portion of the epitaxy layer to form trenches passing through the stacked structure and extending into the epitaxy layer, The stacked structure is divided into a first fin element and a second fin element by the trenches, and the first fin element and the second fin element are over the substrate and the epitaxy layer respectively.
    Type: Application
    Filed: June 24, 2020
    Publication date: October 8, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Winnie Victoria Wei-Ning CHEN, Meng-Hsuan HSIAO, Tung-Ying LEE, Pang-Yen TSAI, Yasutoshi OKUNO
  • Patent number: 10714475
    Abstract: A semiconductor device includes first and second epitaxial structures, first and second top metal alloy layers, and first and second bottom metal alloy layers. The first and second epitaxial structures have different cross sections. The first and second top metal alloy layers are respectively in contact with the first and second epitaxial structures. The first and second bottom metal alloy layers are respectively in contact with the first and second epitaxial structures and respectively under the first and second top metal alloy layers. The first top metal alloy layer and the first bottom metal alloy layer are made of different materials.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: July 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sung-Li Wang, Pang-Yen Tsai, Yasutoshi Okuno
  • Patent number: 10700066
    Abstract: A semiconductor device comprises a substrate having an N-type field effect transistor (NFET) region and a P-type field effect transistor (PFET) region, a plurality of first nanowires in the PFET region and arranged in a first direction substantially perpendicular to the substrate and a plurality of second nanowires in the NFET region and arranged in the first direction. A composition of the first nanowires is different from a composition of the second nanowires, and one of the first nanowires is substantially aligned with one of the second nanowires in a second direction substantially perpendicular to the first direction.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: June 30, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Winnie Victoria Wei-Ning Chen, Meng-Hsuan Hsiao, Tung-Ying Lee, Pang-Yen Tsai, Yasutoshi Okuno
  • Publication number: 20200203342
    Abstract: A method for forming a semiconductor device is provided. The method includes forming a first recess in a substrate. The method includes forming a first semiconductor layer into the first recess. The first semiconductor layer and the substrate are made of different materials, and a first top surface of the first semiconductor layer is lower than a second top surface of the substrate. The method includes forming a second semiconductor layer over the first top surface and the second top surface, wherein a third top surface of the second semiconductor layer over the first top surface is substantially level with the second top surface of the substrate, and the second semiconductor layer and the substrate are made of different materials. The method includes forming a third semiconductor layer over the second semiconductor layer. The third semiconductor layer and the second semiconductor layer are made of different materials.
    Type: Application
    Filed: March 4, 2020
    Publication date: June 25, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Winnie Victoria Wei-Ning CHEN, Meng-Hsuan HSIAO, Tung-Ying LEE, Pang-Yen TSAI, Yasutoshi OKUNO