Patents by Inventor Pao Hung Chou
Pao Hung Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240161957Abstract: Provided is an inductor structure and manufacturing method thereof, including forming an inductance coil in a semiconductor packaging carrier plate and disposing a patterned magnetic conductive layer in the inductance coil. Therefore, a patterned build-up wiring method is used to form a magnetic material in the carrier plate, thereby improving electrical characteristics of the inductor.Type: ApplicationFiled: October 31, 2023Publication date: May 16, 2024Applicant: PHOENIX PIONEER TECHNOLOGY CO., LTD.Inventors: Pao-Hung CHOU, Shih-Ping HSU, Chu-Chin HU
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Publication number: 20240145155Abstract: Provided is a core structure of an inductor element. The manufacturing method thereof is to embed a magnetic conductor including at least one magnetic conductive layer in a core body and to from a plurality of apertures for passing coils around the magnetic conductor in the core body. Accordingly, the magnetic conductor is designed in the core body by using the integrated circuit carrier board manufacturing process, such that the overall size and thickness of the inductor element can be greatly reduced, thereby facilitating product miniaturization using the inductor element.Type: ApplicationFiled: October 31, 2023Publication date: May 2, 2024Applicant: PHOENIX PIONEER TECHNOLOGY CO., LTD.Inventors: Pao-Hung CHOU, Che-Wei HSU, Shih-Ping HSU
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Publication number: 20240136728Abstract: An antenna module is provided, in which an antenna supporting substrate having a step-shaped hollow cavity is disposed on a circuit structure having an antenna part, so that the antenna part is exposed from the step-shaped hollow cavity, and an antenna structure is arranged on the steps of the step-shaped hollow cavity to cover the antenna part and is electromagnetically coupled with the antenna part, and there is no barrier but an air medium between the antenna structure and the antenna part.Type: ApplicationFiled: September 4, 2023Publication date: April 25, 2024Applicant: PHOENIX PIONEER TECHNOLOGY CO., LTD.Inventors: Pao-Hung CHOU, Shih-Ping HSU
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Publication number: 20240055274Abstract: A semiconductor package carrier board structure includes a plurality of carrier board bodies and a plurality of supporting bumps. The carrier board body includes a build-up circuit structure and a plurality of conductive blocks bonded to the build-up circuit structure. Adjacent ones of the carrier board bodies are connected to each other with their corresponding conductive blocks. An area formed by the adjacent conductive blocks defines a cutting path. An opening is formed on a surface of each of the conductive blocks at the cutting path. The supporting bumps are erected between the adjacent openings. As such, each of the supporting bumps corresponds to a position overlapping the cutting path to provide the support function of the semiconductor package carrier board structure when performing the semiconductor packaging operation. After performing the singulation operation, the supporting bumps can be completely removed and one side of the openings can be exposed.Type: ApplicationFiled: August 15, 2023Publication date: February 15, 2024Applicant: PHOENIX PIONEER TECHNOLOGY CO., LTD.Inventors: Pao-Hung CHOU, Ming-Yeh CHANG
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Patent number: 11791281Abstract: A package substrate and method of manufacturing a package substrate and a semiconductor device package are provided. The package substrate includes a circuit layer, a molding layer and a sacrificial layer. The circuit layer includes conductive traces and conductive pads. The molding layer has an upper surface and a lower surface opposite to the upper surface, wherein the molding layer partially covers the conductive traces and the conductive pads, and first surfaces of the conductive traces and first surfaces of the conductive pads are exposed from the upper surface of the molding layer. The sacrificial layer covers the lower surface of the molding layer, second surfaces of the conductive pads.Type: GrantFiled: March 19, 2020Date of Patent: October 17, 2023Assignees: ADVANCED SEMICONDUCTOR ENGINEERING, INC., PHOENIX PIONEER TECHNOLOGY CO., LTD.Inventors: You-Lung Yen, Pao-Hung Chou, Chun-Hsien Yu
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Patent number: 11749619Abstract: A package substrate and method of manufacturing a package substrate and a semiconductor device package are provided. The package substrate includes a circuit layer, a molding layer and a sacrificial layer. The circuit layer includes conductive traces and conductive pads. The molding layer has an upper surface and a lower surface opposite to the upper surface, wherein the molding layer partially covers the conductive traces and the conductive pads, and first surfaces of the conductive traces and first surfaces of the conductive pads are exposed from the upper surface of the molding layer. The sacrificial layer covers the lower surface of the molding layer, second surfaces of the conductive pads.Type: GrantFiled: March 19, 2020Date of Patent: September 5, 2023Assignees: ADVANCED SEMICONDUCTOR ENGINEERING, INC., PHOENIX PIONEER TECHNOLOGY CO., LTD.Inventors: You-Lung Yen, Pao-Hung Chou, Chun-Hsien Yu
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Patent number: 11658104Abstract: An intermediate substrate is provided with a plurality of conductive posts and support members arranged at opposite sides of a coreless circuit structure and insulating layers encapsulating the conductive posts and the support members. Through the arrangement of the support members and the insulating layers, the intermediate substrate can meet the rigidity requirement so as to effectively resist warping and achieve an application of fine-pitch circuits.Type: GrantFiled: February 24, 2022Date of Patent: May 23, 2023Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.Inventors: Shih-Ping Hsu, Chu-Chin Hu, Pao-Hung Chou
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Publication number: 20220406734Abstract: A flip-chip packaging substrate and a method for fabricating the same are disclosed. The method includes stacking a plurality of insulating layers having conductive posts in a manner that the conductive posts are stacked on and in contact with one another. The insulating layers and the conductive posts serve as a core layer structure of the flip-chip packaging substrate. As such, the conductive posts having small-sized end surfaces can be fabricated according to the practical need. Therefore, when the thickness of the core layer structure is increased, the present disclosure not only increases the rigidity of the flip-chip packaging substrate so as to avoid warping, but also ensures the design flexibility of the small-sized end surfaces of the conductive posts, allowing high-density electrical connection points and fine-pitch and high-density circuit layers to be fabricated on the core layer structure.Type: ApplicationFiled: August 19, 2022Publication date: December 22, 2022Inventors: Pao-Hung Chou, Chun-Hsien Yu, Shih-Ping Hsu, Tung-Yao Kuo
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Patent number: 11508673Abstract: A semiconductor packaging substrate is provided and includes: an insulating layer, a thinned circuit structure formed of circuit layers and conductive posts stacked on one another embedding in the insulating layer, and a supporting structure formed on the insulating layer and having at least one through hole exposing the conductive posts. As such, before a subsequent packaging operation, the packaging substrate can be electrically tested and screened so as to prevent a defective packaging substrate from being misused in the subsequent packaging operation and hence avoid the loss of normal electronic elements. A method for fabricating a semiconductor packaging substrate and a packaging process using the semiconductor packaging substrate are also provided.Type: GrantFiled: March 16, 2021Date of Patent: November 22, 2022Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.Inventors: Pao-Hung Chou, Chun-Hsien Yu
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Patent number: 11476204Abstract: A flip-chip packaging substrate and a method for fabricating the same are disclosed. The method includes stacking a plurality of insulating layers having conductive posts in a manner that the conductive posts are stacked on and in contact with one another. The insulating layers and the conductive posts serve as a core layer structure of the flip-chip packaging substrate. As such, the conductive posts having small-sized end surfaces can be fabricated according to the practical need. Therefore, when the thickness of the core layer structure is increased, the present disclosure not only increases the rigidity of the flip-chip packaging substrate so as to avoid warping, but also ensures the design flexibility of the small-sized end surfaces of the conductive posts, allowing high-density electrical connection points and fine-pitch and high-density circuit layers to be fabricated on the core layer structure.Type: GrantFiled: May 7, 2019Date of Patent: October 18, 2022Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.Inventors: Pao-Hung Chou, Chun-Hsien Yu, Shih-Ping Hsu, Tung-Yao Kuo
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Publication number: 20220328613Abstract: An inductance structure is provided and includes a plurality of inductance traces embedded in an insulating body and at least one shielding layer that is embedded in the insulating body and free from being electrically connected to the inductance traces. The shielding layer has a plurality of line segments that are free from being connected to one another. The shielding layer shields the inductance traces to improve the inductance value and quality factor.Type: ApplicationFiled: March 4, 2022Publication date: October 13, 2022Inventors: Pao-Hung Chou, Chun-Hsien Yu, Shih-Ping Hsu
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Patent number: 11450597Abstract: A semiconductor package substrate, a method for fabricating the same, and an electronic package having the same are provided. The method includes: providing a circuit structure having a first solder pad and a second solder pad; forming on the circuit structure a metal sheet having a first hole, from which the first solder pad is exposed, and a second hole, from which the second solder pad is exposed; and forming an insulation layer on the metal sheet and a hole wall of the second hole. A first conductive element that is to be grounded is disposed in the first hole and is in contact with the metal sheet and the first solder pad. Therefore, heat generated in a signal transmission process is dissipated by the metal sheet and the first conductive element.Type: GrantFiled: June 10, 2020Date of Patent: September 20, 2022Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.Inventors: Pao-Hung Chou, Chun-Hsien Yu, Shih-Ping Hsu
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Publication number: 20220285257Abstract: An intermediate substrate is provided with a plurality of conductive posts and support members arranged at opposite sides of a coreless circuit structure and insulating layers encapsulating the conductive posts and the support members. Through the arrangement of the support members and the insulating layers, the intermediate substrate can meet the rigidity requirement so as to effectively resist warping and achieve an application of fine-pitch circuits.Type: ApplicationFiled: February 24, 2022Publication date: September 8, 2022Inventors: Shih-Ping Hsu, Chu-Chin Hu, Pao-Hung Chou
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Patent number: 11404348Abstract: A semiconductor package carrier board, a method for fabricating the same, and an electronic package having the same are provided. The method includes forming on a circuit structure a graphene layer that acts as an insulation heat dissipating layer. Since the heat conductivity of the graphene layer is far greater than the heat conductivity of ink (about 0.4 W/m·k), which is used as solder resist, the heat of the semiconductor package carrier board can be conducted quickly, and thus can avoid the problem that the heat will be accumulated on the semiconductor package carrier board.Type: GrantFiled: June 5, 2020Date of Patent: August 2, 2022Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.Inventors: Pao-Hung Chou, Chun-Hsien Yu, Shih-Ping Hsu, Wen-Chang Chen
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Patent number: 11335630Abstract: A semiconductor packaging substrate and a method for fabricating the same are provided. The method includes forming a solder resist structure having a hole on a circuit structure, with a portion of the circuit structure exposed from the hole, and forming a cup-shaped solder stand on the exposed circuit layer and a hole wall of the hole. During a packaging process, the design of the solder stand increases a contact area of a solder tin ball with a metal material. Therefore, a bonding force between the solder tin ball and the solder stand is increased, and the solder tin ball can be protected from being broken or fell off. An electronic package having the semiconductor packaging substrate and a method for fabricating the electronic package are also provided.Type: GrantFiled: March 27, 2020Date of Patent: May 17, 2022Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.Inventors: Pao-Hung Chou, Chun-Hsien Yu, Shih-Ping Hsu
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Patent number: 11183447Abstract: A flip-chip package substrate and a method for fabricating the same are provided. An insulation layer is formed on two opposing sides of a middle layer to form a composite core structure and increase the rigidity of the flip-chip package substrate. Therefore, the core structure can be made thinner. The conductive structures can also have a smaller end size, and more conductive points can be disposed within a unit area. Therefore, a circuit structure can be produced that have a fine line pitch and a high wiring density, satisfy the packaging demands of highly integrated circuit/large size substrate, and avoid an electronic package from being warpage.Type: GrantFiled: September 15, 2020Date of Patent: November 23, 2021Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.Inventors: Pao-Hung Chou, Chun-Hsien Yu, Shih-Ping Hsu
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Patent number: 11139230Abstract: A flip-chip package substrate and a method for preparing the same in accordance with the present disclosure includes stacking a reinforcement layer on two opposing sides of a middle layer in order to increase the rigidity of the flip-chip package substrate, and promoting a thin middle layer, wherein the sizes of the end faces of conductive portions can be minimized according to needs. This increases the number of electrical contacts possible in a unit area and enables the creation of finer line pitch and higher layout density of the circuit portions, thereby satisfying the need for packaging of high integration/large scale chips while preventing warpage from occurring in the electronic packages.Type: GrantFiled: August 16, 2019Date of Patent: October 5, 2021Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.Inventors: Pao-Hung Chou, Chun-Hsien Yu, Shih-Ping Hsu
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Publication number: 20210296259Abstract: A package substrate and method of manufacturing a package substrate and a semiconductor device package are provided. The package substrate includes a circuit layer, a molding layer and a sacrificial layer. The circuit layer includes conductive traces and conductive pads. The molding layer has an upper surface and a lower surface opposite to the upper surface, wherein the molding layer partially covers the conductive traces and the conductive pads, and first surfaces of the conductive traces and first surfaces of the conductive pads are exposed from the upper surface of the molding layer. The sacrificial layer covers the lower surface of the molding layer, second surfaces of the conductive pads.Type: ApplicationFiled: March 19, 2020Publication date: September 23, 2021Applicants: Advanced Semiconductor Engineering, Inc., Phoenix Pioneer Technology Co., Ltd.Inventors: You-Lung YEN, Pao-Hung CHOU, Chun-Hsien YU
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Publication number: 20210296260Abstract: A semiconductor packaging substrate is provided and includes: an insulating layer, a thinned circuit structure formed of circuit layers and conductive posts stacked on one another embedding in the insulating layer, and a supporting structure formed on the insulating layer and having at least one through hole exposing the conductive posts. As such, before a subsequent packaging operation, the packaging substrate can be electrically tested and screened so as to prevent a defective packaging substrate from being misused in the subsequent packaging operation and hence avoid the loss of normal electronic elements. A method for fabricating a semiconductor packaging substrate and a packaging process using the semiconductor packaging substrate are also provided.Type: ApplicationFiled: March 16, 2021Publication date: September 23, 2021Inventors: Pao-Hung Chou, Chun-Hsien Yu
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Patent number: 11069540Abstract: A method for fabricating an interposer substrate is provided, including forming a wiring layer on a carrier, forming an insulating layer on the carrier, forming on the wiring layer a wiring build-up layer structure that is electrically connected to the wiring layer, forming on the wiring build-up layer structure external connection pillars that are electrically connected to the wiring build-up layer structure, and removing the carrier, with the wiring layer is exposed from a surface of the insulating layer. The fabrication process of the via can be bypassed in the fabrication process by forming coreless interposer substrate on the carrier, such that the overall cost of the fabrication process can be decreased, and the fabrication process is simple. This invention further provides the interposer substrate.Type: GrantFiled: November 19, 2014Date of Patent: July 20, 2021Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.Inventor: Pao-Hung Chou