Patents by Inventor Pao-Ling Koh
Pao-Ling Koh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10971199Abstract: A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The control circuit is configured to control the non-volatile memory structure to perform memory operations by generating and applying a set of control signals to the non-volatile memory structure The control circuit includes a programmable and reprogrammable microcontroller. For example, the microcontroller includes one or more processors that are programmed using software (e.g., firmware). The use of a programmable processor and software allows for updates and changes to be made easily. Additionally, to reduce the time taken to make some calculations, the microcontroller also includes one or more combinational logic circuits that are in communication with the one or more processors.Type: GrantFiled: June 20, 2019Date of Patent: April 6, 2021Assignee: SANDISK TECHNOLOGIES LLCInventors: Pao-Ling Koh, Yuheng Zhang, Yan Li
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Publication number: 20200402553Abstract: A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The control circuit is configured to control the non-volatile memory structure to perform memory operations by generating and applying a set of control signals to the non-volatile memory structure The control circuit includes a programmable and reprogrammable microcontroller. For example, the microcontroller includes one or more processors that are programmed using software (e.g., firmware). The use of a programmable processor and software allows for updates and changes to be made easily. Additionally, to reduce the time taken to make some calculations, the microcontroller also includes one or more combinational logic circuits that are in communication with the one or more processors.Type: ApplicationFiled: June 20, 2019Publication date: December 24, 2020Applicant: SANDISK TECHNOLOGIES LLCInventors: Pao-Ling Koh, Yuheng Zhang, Yan Li
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Patent number: 10007311Abstract: A storage device with a memory may modify throttling to reduce cross temperature effects. The decision to throttle may be based on a memory device temperature (i.e. temperature throttling) or may be based on the memory device's health, usage, or performance (e.g. hot count or bit error rate). Temperature throttling may be implemented that considers the memory device's health, usage, or performance (e.g. hot count or bit error rate). Likewise, throttling based on the memory device's health, usage, or performance may utilize the memory device's temperature to optimize throttling time. For example, a test mode matrix (TMM) may be modified to depend on temperature.Type: GrantFiled: August 15, 2016Date of Patent: June 26, 2018Assignee: SanDisk Technologies LLCInventors: Deepak Raghu, Pao-Ling Koh, Philip Reusswig, Chris Nga Yee Yip, Jun Wan, Yan Li
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Patent number: 9911500Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage (Vth) of a memory cell can shift depending on when the read operation occurs. In one aspect, a dummy voltage is applied to the word lines to cause a coupling up of the word lines and weak programming. This can occur when a specified amount of time has elapsed since a last program or read operation, or when a power on event is detected for the memory device. A number of read errors can also be considered. The dummy voltage is similar to a pass voltage of a program or read operation but no sensing is performed. The word line voltages are therefore provided at a consistently up-coupled level so that read operations are consistent. The coupling up occurs due to capacitive coupling between the word line and the channel.Type: GrantFiled: April 18, 2016Date of Patent: March 6, 2018Assignee: SanDisk Technologies LLCInventors: Liang Pang, Pao-ling Koh, Jiahui Yuan, Charles Kwong, Yingda Dong
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Publication number: 20180046231Abstract: A storage device with a memory may modify throttling to reduce cross temperature effects. The decision to throttle may be based on a memory device temperature (i.e. temperature throttling) or may be based on the memory device's health, usage, or performance (e.g. hot count or bit error rate). Temperature throttling may be implemented that considers the memory device's health, usage, or performance (e.g. hot count or bit error rate). Likewise, throttling based on the memory device's health, usage, or performance may utilize the memory device's temperature to optimize throttling time. For example, a test mode matrix (TMM) may be modified to depend on temperature.Type: ApplicationFiled: August 15, 2016Publication date: February 15, 2018Applicant: SanDisk Technologies LLCInventors: Deepak Raghu, Pao-Ling Koh, Philip Reusswig, Chris Nga Yee Yip, Jun Wan, Yan Li
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Publication number: 20170301403Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage (Vth) of a memory cell can shift depending on when the read operation occurs. In one aspect, a dummy voltage is applied to the word lines to cause a coupling up of the word lines and weak programming. This can occur when a specified amount of time has elapsed since a last program or read operation, or when a power on event is detected for the memory device. A number of read errors can also be considered. The dummy voltage is similar to a pass voltage of a program or read operation but no sensing is performed. The word line voltages are therefore provided at a consistently up-coupled level so that read operations are consistent. The coupling up occurs due to capacitive coupling between the word line and the channel.Type: ApplicationFiled: April 18, 2016Publication date: October 19, 2017Applicant: SanDisk Technologies Inc.Inventors: Liang Pang, Pao-ling Koh, Jiahui Yuan, Charles Kwong, Yingda Dong
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Patent number: 9785357Abstract: Systems and methods for sampling data at a non-volatile memory system are disclosed. In one implementation, a controller of a non-volatile memory system that is coupled with a host device acquires a read level voltage of a first word line of a memory block of a non-volatile memory of the non-volatile memory system. The controller accesses one or more lookup tables to determine an offset voltage for a second word line of the memory block based on a program/erase count and a read/disturb count associated with the memory block; applies the read level voltage and the offset voltage to the second word line to sample data stored at the memory block; and determines whether the data sampled from the memory block contains errors.Type: GrantFiled: October 20, 2015Date of Patent: October 10, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Deepak Raghu, Chris Aviala, Harish Singidi, Guirong Liang, Anne Pao-Ling Koh, Dana Lee, Gautam Dusija
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Patent number: 9741444Abstract: Methods and systems are provided where non-volatile solid state memory may include selected memory cells coupled to a selected word line and proxy memory cells coupled to a proxy word line. The selected memory cells may be non-adjacent to the proxy memory cells and be selected for a read operation. A read proxy voltage may be applied to the proxy word line when data is read from the selected memory cells. A read disturb may be determined based on a difference between a predetermined value stored in the proxy memory cells and a value read from the proxy memory cells.Type: GrantFiled: April 10, 2017Date of Patent: August 22, 2017Assignee: SanDisk Technologies LLCInventors: Philip Reusswig, Harish Singidi, Deepak Raghu, Gautam Dusija, Pao-Ling Koh, Chris Avila
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Publication number: 20170213599Abstract: Methods and systems are provided where non-volatile solid state memory may include selected memory cells coupled to a selected word line and proxy memory cells coupled to a proxy word line. The selected memory cells may be non-adjacent to the proxy memory cells and be selected for a read operation. A read proxy voltage may be applied to the proxy word line when data is read from the selected memory cells. A read disturb may be determined based on a difference between a predetermined value stored in the proxy memory cells and a value read from the proxy memory cells.Type: ApplicationFiled: April 10, 2017Publication date: July 27, 2017Inventors: Philip Reusswig, Harish Singidi, Deepak Raghu, Gautam Dusija, Pao-Ling Koh, Chris Avila
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Patent number: 9646709Abstract: Methods and systems are provided where non-volatile solid state memory may include selected memory cells coupled to a selected word line and proxy memory cells coupled to a proxy word line. The selected memory cells may be non-adjacent to the proxy memory cells and be selected for a read operation. A read proxy voltage may be applied to the proxy word line when data is read from the selected memory cells. A read disturb may be determined based on a difference between a predetermined value stored in the proxy memory cells and a value read from the proxy memory cells.Type: GrantFiled: September 11, 2015Date of Patent: May 9, 2017Assignee: SanDisk Technologies, LLCInventors: Philip Reusswig, Harish Singidi, Deepak Raghu, Gautam Dusija, Pao-Ling Koh, Chris Avila
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Patent number: 9633738Abstract: A storage system includes a controller that is configured to make host data inaccessible. To do so, the controller may control power control circuitry to supply pulses to storage locations storing host data. The pulses may include flash write pulses but no erase pulses, or a combination of flash write pulses and erase pulses. If erase pulses are supplied, the number of the erase pulses may be less than the number supplied for performance of a default erase operation.Type: GrantFiled: June 28, 2016Date of Patent: April 25, 2017Assignee: SanDisk Technologies LLCInventors: Zelei Guo, Pao-Ling Koh, Henry Chin, Pitamber Shukla, Deepak Raghu, Dana Lee
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Publication number: 20170109040Abstract: Systems and methods for sampling data at a non-volatile memory system are disclosed. In one implementation, a controller of a non-volatile memory system that is coupled with a host device acquires a read level voltage of a first word line of a memory block of a non-volatile memory of the non-volatile memory system. The controller accesses one or more lookup tables to determine an offset voltage for a second word line of the memory block based on a program/erase count and a read/disturb count associated with the memory block; applies the read level voltage and the offset voltage to the second word line to sample data stored at the memory block; and determines whether the data sampled from the memory block contains errors.Type: ApplicationFiled: October 20, 2015Publication date: April 20, 2017Applicant: SANDISK TECHNOLOGIES INC.Inventors: Deepak Raghu, Chris Aviala, Harish Singidi, Guirong Liang, Anne Pao-LIng Koh, Dana Lee, Gautam Dusija
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Publication number: 20170076811Abstract: Methods and systems are provided where non-volatile solid state memory may include selected memory cells coupled to a selected word line and proxy memory cells coupled to a proxy word line. The selected memory cells may be non-adjacent to the proxy memory cells and be selected for a read operation. A read proxy voltage may be applied to the proxy word line when data is read from the selected memory cells. A read disturb may be determined based on a difference between a predetermined value stored in the proxy memory cells and a value read from the proxy memory cells.Type: ApplicationFiled: September 11, 2015Publication date: March 16, 2017Inventors: Philip Reusswig, Harish Singidi, Deepak Raghu, Gautam Dusija, Pao-Ling Koh, Chris Avila
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Patent number: 9582435Abstract: In one embodiment, a memory system is provided comprising a memory die and a controller. The memory die comprises a non-volatile memory, a data latch, and an on-chip randomizer. The controller is configured to send a command to the memory die to cause the on-chip randomizer to store random data in the data latch and send data to the memory die to overwrite some, but not all, of the random data in the data latch, wherein the memory die is configured to transfer the data and random data stored in the data latch to the non-volatile memory. Other embodiments are provided.Type: GrantFiled: March 23, 2015Date of Patent: February 28, 2017Assignee: SanDisk Technologies LLCInventors: Vimal Jain, Abhijeet Manohar, Aaron Lee, Anne Pao-Ling Koh
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Publication number: 20160283110Abstract: In one embodiment, a memory system is provided comprising a memory die and a controller. The memory die comprises a non-volatile memory, a data latch, and an on-chip randomizer. The controller is configured to send a command to the memory die to cause the on-chip randomizer to store random data in the data latch and send data to the memory die to overwrite some, but not all, of the random data in the data latch, wherein the memory die is configured to transfer the data and random data stored in the data latch to the non-volatile memory. Other embodiments are provided.Type: ApplicationFiled: March 23, 2015Publication date: September 29, 2016Applicant: SanDisk Technologies Inc.Inventors: Vimal Jain, Abhijeet Manohar, Aaron Lee, Anne Pao-Ling Koh
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Patent number: 9431120Abstract: A memory die is provided comprising a non-volatile memory organized in physical pages, a transfer data latch in communication with the non-volatile memory, at least one auxiliary data latch in communication with the transfer data latch, and circuitry. The circuitry is configured to receive a plurality of sense commands, wherein each sense command indicates a physical page in the non-volatile memory to be sensed and a portion of the physical page to be stored in the at least one auxiliary data latch. For each sense command, the circuitry is configured to store data from the physical page sensed by the sense command in the transfer data latch and move data from the portion of the physical page indicated by the sense command to an available location in the at least one auxiliary data latch.Type: GrantFiled: March 23, 2015Date of Patent: August 30, 2016Assignee: SanDisk Technologies, LLCInventors: Daniel E. Tuers, Anne Pao-Ling Koh, Abhijeet Manohar
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Patent number: 9218886Abstract: In a three-dimensional NAND memory in which a block contains multiple separately-selectable sets of strings connected to the same set of bit lines, sets of strings are zoned, and different operating parameters applied to different zones. Operating parameters for a zone are obtained from characterizing a reference set of strings in the zone.Type: GrantFiled: December 10, 2013Date of Patent: December 22, 2015Assignee: SanDisk Technologies, Inc.Inventors: Gautam A. Dusija, Yingda Dong, Chris Avila, Deepak Raghu, Pao-Ling Koh
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Patent number: 9177673Abstract: Layers in a multi-layer memory array are categorized according to likely error rates as predicted from their memory hole diameters. Data to be stored along a word line in a high risk layer is subject to a redundancy operation (e.g. XOR) with data to be stored along a word line in a low risk layer so that the risk of both being bad is low.Type: GrantFiled: October 28, 2013Date of Patent: November 3, 2015Assignee: SanDisk Technologies Inc.Inventors: Deepak Raghu, Gautam A. Dusija, Chris Avila, Yingda Dong, Man Mui, Xiying Costa, Pao-Ling Koh
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Patent number: 9136022Abstract: Layers in a multi-layer memory array are categorized according to likely error rates as predicted from their memory hole diameters. Data to be stored along a word line in a high risk layer is subject to a redundancy operation (e.g. XOR) with data to be stored along a word line in a low risk layer so that the risk of both being bad is low.Type: GrantFiled: May 22, 2014Date of Patent: September 15, 2015Assignee: SanDisk Technologies Inc.Inventors: Deepak Raghu, Gautam A. Dusija, Chris Avila, Yingda Dong, Man Mui, Xiying Costa, Pao-Ling Koh
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Patent number: 9129701Abstract: Techniques are disclosed herein for determining whether there is a defect that occurred as a result of programming non-volatile storage elements. Example defects include: broken word lines, control gate to substrate shorts, word line to word line shorts, double writes, etc. The memory cells may be programmed such that there will be a substantially even distribution of the memory cells in different data states. After programming, the memory cells are sensed at one or more reference levels. Two sub-groups of memory cells are strategically formed based on the sensing to enable detection of defects in a simple and efficient manner. The sub-groups may have a certain degree of separation of the data states to avoid missing a defect. The number of memory cells in one sub-group is compared with the other. If there is a significant imbalance between the two sub-groups, then a defect is detected.Type: GrantFiled: December 19, 2013Date of Patent: September 8, 2015Assignee: SanDisk Technologies Inc.Inventors: Rohan Patel, Eugene Tam, Pao-Ling Koh