Abstract: Techniques are disclosed herein for determining whether there is a defect that occurred as a result of programming non-volatile storage elements. Example defects include: broken word lines, control gate to substrate shorts, word line to word line shorts, double writes, etc. The memory cells may be programmed such that there will be a substantially even distribution of the memory cells in different data states. After programming, the memory cells are sensed at one or more reference levels. Two sub-groups of memory cells are strategically formed based on the sensing to enable detection of defects in a simple and efficient manner. The sub-groups may have a certain degree of separation of the data states to avoid missing a defect. The number of memory cells in one sub-group is compared with the other. If there is a significant imbalance between the two sub-groups, then a defect is detected.

Abstract: Data that is stored in a higher error rate format in a nonvolatile memory is backed up in a lower error rate format. Data to be stored may be transferred once to on-chip data latches where it is maintained while it is programmed in both the high error rate format and the low error rate format without being resent to the nonvolatile memory. High error rate format may be MLC format and programming in the high error rate format may program both lower page and upper page data together in a full sequence programming scheme that is suitable for handling high data volume.

Abstract: Multiple bits of data are programmed together to each cell of a segment of a word line while other segments of the same word line are unprogrammed. Subsequently, additional segments are similarly programmed. Data is read from a partially programmed word line (with a mix of programmed and unprogrammed segments) using a single reading scheme.

Abstract: In a three-dimensional NAND memory in which a block contains multiple separately-selectable sets of strings connected to the same set of bit lines, sets of strings are zoned, and different operating parameters applied to different zones. Operating parameters for a zone are obtained from characterizing a reference set of strings in the zone.

Abstract: Multiple bits of data are programmed together to each cell of a segment of a word line while other segments of the same word line are unprogrammed. Subsequently, additional segments are similarly programmed. Data is read from a partially programmed word line (with a mix of programmed and unprogrammed segments) using a single reading scheme.

Abstract: Memory hole diameter in a three dimensional memory array may be calculated from characteristics that are observed during programming. Suitable operating parameters may be selected for operating a block based on memory hole diameters. Hot counts of blocks may be adjusted according to memory hole size so that blocks that are expected to fail earlier because of small memory holes are more lightly used than blocks with larger memory holes.

Abstract: Layers in a multi-layer memory array are categorized according to likely error rates as predicted from their memory hole diameters. Data to be stored along a word line in a high risk layer is subject to a redundancy operation (e.g. XOR) with data to be stored along a word line in a low risk layer so that the risk of both being bad is low.

Abstract: Layers in a multi-layer memory array are categorized according to likely error rates as predicted from their memory hole diameters. Data to be stored along a word line in a high risk layer is subject to a redundancy operation (e.g. XOR) with data to be stored along a word line in a low risk layer so that the risk of both being bad is low.

Abstract: In a three-dimensional NAND memory in which a block contains multiple separately-selectable sets of strings connected to the same set of bit lines, sets of strings are zoned, and different operating parameters applied to different zones. Operating parameters for a zone are obtained from characterizing a reference set of strings in the zone.

Abstract: Multiple bits of data are programmed together to each cell of a segment of a word line while other segments of the same word line are unprogrammed. Subsequently, additional segments are similarly programmed. Data is read from a partially programmed word line (with a mix of programmed and unprogrammed segments) using a single reading scheme.

Abstract: Data that is stored in a higher error rate format in a nonvolatile memory is backed up in a lower error rate format. Data to be stored may be transferred once to on-chip data latches where it is maintained while it is programmed in both the high error rate format and the low error rate format without being resent to the nonvolatile memory. High error rate format may be MLC format and programming in the high error rate format may program both lower page and upper page data together in a full sequence programming scheme that is suitable for handling high data volume.

Abstract: Erasing memory cells in certain 3-D NAND charge-storage memory arrays is achieved by rapidly charging vertical conductors using Gate Induced Drain Leakage (GIDL) current generated in select transistors. When bit line voltage drops below its nominal value, select line voltage is controlled to maintain a constant voltage difference between bit line voltage and select line voltage thus maintaining a gate-drain voltage difference in select transistors that provides sufficient GIDL current for erase.

Abstract: Memory hole diameter in a three dimensional memory array may be calculated from characteristics that are observed during programming. Suitable operating parameters may be selected for operating a block based on memory hole diameters. Hot counts of blocks may be adjusted according to memory hole size so that blocks that are expected to fail earlier because of small memory holes are more lightly used than blocks with larger memory holes.

Abstract: Erasing memory cells in certain 3-D NAND charge-storage memory arrays is achieved by rapidly charging vertical conductors using Gate Induced Drain Leakage (GIDL) current generated in select transistors. When bit line voltage drops below its nominal value, select line voltage is controlled to maintain a constant voltage difference between bit line voltage and select line voltage thus maintaining a gate-drain voltage difference in select transistors that provides sufficient GIDL current for erase.

Abstract: Technique of operating a non-volatile memory are presented so that in case data that would otherwise be lost in the case of a word line to word line short is preserved. Before writing a word line, the data from a previously written adjacent is word line is read back and stored in data latches associated with the corresponding bit lines, but that are not being used for the data to be written. If a short occurs, as the data for both word lines is still in the latches, it can be written to a new location. This technique can also be incorporated into cache write operations and for a binary write operation inserted into a pause of a multi-state write.

Abstract: Technique of operating a non-volatile memory are presented so that in case data that would otherwise be lost in the case of a word line to word line short is preserved. Before writing a word line, the data from a previously written adjacent is word line is read back and stored in data latches associated with the corresponding bit lines, but that are not being used for the data to be written. If a short occurs, as the data for both word lines is still in the latches, it can be written to a new location. This technique can also be incorporated into cache write operations and for a binary write operation inserted into a pause of a multi-state write.

Abstract: A memory system or flash card may include a multi-level cell block with multiple states. Before the upper page is written, an intermediate state may be shifted to prevent or minimize overlapping of the states from the corresponding lower page. A write abort during the writing of the upper page will not result in a loss of data from the corresponding lower page.

Abstract: In a non-volatile storage system, the time needed to perform a programming operation is reduced by minimizing data transfers between sense modules and a managing circuit. A sense module is associated with each storage element. Based on write data, a data node in the sense module is initialized to “0” for a storage element which is to remain in an erased state, and to “1” for a storage element which is to be programmed to a programmed state, then flipped to “0” when programmed is completed. The managing circuit is relieved of the need to access the write data to determine whether a “0” represents a storage element for which programming is completed. Power consumption can also be reduced by keeping a bit line voltage high between a verify phase of one program-verify iteration and a program phase of a next program-verify iteration.

Abstract: In a non-volatile storage system, the time needed to perform a programming operation is reduced by minimizing data transfers between sense modules and a managing circuit. A sense module is associated with each storage element. Based on write data, a data node in the sense module is initialized to “0” for a storage element which is to remain in an erased state, and to “1” for a storage element which is to be programmed to a programmed state, then flipped to “0” when programmed is completed. The managing circuit is relieved of the need to access the write data to determine whether a “0” represents a storage element for which programming is completed. Power consumption can also be reduced by keeping a bit line voltage high between a verify phase of one program-verify iteration and a program phase of a next program-verify iteration.

Abstract: A non-volatile memory can perform a first operation (such as a write, for example) on a designated group of one or more addressed pages using a first set of data stored in the corresponding set of data latches and also receive a request for a second operation (such as a read, for example) that also uses some of these corresponding data latches with a second set of data. During the first operation, when at least one latch of each set of the corresponding become available for the second operation, the memory whether there are a sufficient number of the corresponding set of data latches to perform the second operation during the first operation; if not, the second operation is delayed.