Patents by Inventor Paolo Giuseppe Cappelletti
Paolo Giuseppe Cappelletti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230389450Abstract: Phase-change memory cells and methods of manufacturing and operating phase-change memory cells are provided. In at least one embodiment, a phase-change memory cell includes a heater and a stack. The stack includes at least one germanium layer or a nitrogen doped germanium layer, and at least one layer of a first alloy including germanium, antimony, and tellurium. A resistive layer is located between the heater and the stack.Type: ApplicationFiled: April 21, 2023Publication date: November 30, 2023Applicants: STMICROELECTRONICS S.r.l., COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Paolo Giuseppe CAPPELLETTI, Gabriele NAVARRO
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Patent number: 11653579Abstract: Phase-change memory cells and methods of manufacturing and operating phase-change memory cells are provided. In at least one embodiment, a phase-change memory cell includes a heater and a stack. The stack includes at least one germanium layer or a nitrogen doped germanium layer, and at least one layer of a first alloy including germanium, antimony, and tellurium. A resistive layer is located between the heater and the stack.Type: GrantFiled: February 3, 2021Date of Patent: May 16, 2023Inventors: Paolo Giuseppe Cappelletti, Gabriele Navarro
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Patent number: 11641786Abstract: A phase-change memory cell includes, in at least a first portion, a stack of at least one germanium layer covered by at least one layer made of a first alloy of germanium, antimony, and tellurium In a programmed state, resulting from heating a portion of the stack to a sufficient temperature, portions of layers of germanium and of the first alloy form a second alloy made up of germanium, antimony, and tellurium, where the second alloy has a higher germanium concentration than the first alloy.Type: GrantFiled: June 6, 2022Date of Patent: May 2, 2023Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES, STMicroelectronics S.r.l.Inventors: Paolo Giuseppe Cappelletti, Gabriele Navarro
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Publication number: 20230032898Abstract: A memory cell includes a substrate with a semiconductor region and an insulating region. A first insulating layer extends over the substrate. A phase change material layer rests on the first insulating layer. The memory cell further includes an interconnection network with a conductive track. A first end of a first conductive via extending through the first insulating layer is in contact with the phase change material layer and a second end of the first conductive via is in contact with the semiconductor region. A first end of a second conductive via extending through the first insulating layer is in contact with both the phase change material layer and the conductive track, and a second end of the second conductive via is in contact only with the insulating region.Type: ApplicationFiled: July 27, 2022Publication date: February 2, 2023Applicants: STMicroelectronics S.r.l., STMicroelectronics (Crolles 2) SASInventors: Paolo Giuseppe CAPPELLETTI, Fausto PIAZZA, Andrea REDAELLI
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Publication number: 20220302379Abstract: A phase-change memory cell includes, in at least a first portion, a stack of at least one germanium layer covered by at least one layer made of a first alloy of germanium, antimony, and tellurium In a programmed state, resulting from heating a portion of the stack to a sufficient temperature, portions of layers of germanium and of the first alloy form a second alloy made up of germanium, antimony, and tellurium, where the second alloy has a higher germanium concentration than the first alloy.Type: ApplicationFiled: June 6, 2022Publication date: September 22, 2022Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES, STMicroelectronics S.r.l.Inventors: Paolo Giuseppe CAPPELLETTI, Gabriele NAVARRO
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Publication number: 20220238603Abstract: An electronic cell includes an integrated stack of structures including, successively: a first electrode; an ovonic threshold switch layer below the first electrode; and a fixed resistor below the ovonic threshold switch layer. A second electrode may be included between fixed resistor and the ovonic threshold switch layer. A memory layer, for example a phase change material layer, a resistive random-access memory layer or a magneto-resistive random-access memory layer, may be included between the first electrode and the ovonic threshold switch layer.Type: ApplicationFiled: January 21, 2022Publication date: July 28, 2022Applicant: STMicroelectronics S.r.l.Inventors: Paolo Giuseppe CAPPELLETTI, Andrea REDAELLI
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Patent number: 11355702Abstract: A phase-change memory cell includes, in at least a first portion, a stack of at least one germanium layer covered by at least one layer made of a first alloy of germanium, antimony, and tellurium In a programmed state, resulting from heating a portion of the stack to a sufficient temperature, portions of layers of germanium and of the first alloy form a second alloy made up of germanium, antimony, and tellurium, where the second alloy has a higher germanium concentration than the first alloy.Type: GrantFiled: August 6, 2019Date of Patent: June 7, 2022Assignees: STMicroelectronics S.r.l., Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Paolo Giuseppe Cappelletti, Gabriele Navarro
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Patent number: 11227992Abstract: A phase-change memory cell is formed by a heater, a crystalline layer disposed above the heater, and an insulating region surrounding sidewalls of the crystalline layer. The phase-change memory cell supports programming with a least three distinct data levels based on a selective amorphization of the crystalline layer.Type: GrantFiled: May 26, 2020Date of Patent: January 18, 2022Assignee: STMicroelectronics S.r.l.Inventor: Paolo Giuseppe Cappelletti
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Publication number: 20210249594Abstract: Phase-change memory cells and methods of manufacturing and operating phase-change memory cells are provided. In at least one embodiment, a phase-change memory cell includes a heater and a stack. The stack includes at least one germanium layer or a nitrogen doped germanium layer, and at least one layer of a first alloy including germanium, antimony, and tellurium. A resistive layer is located between the heater and the stack.Type: ApplicationFiled: February 3, 2021Publication date: August 12, 2021Inventors: Paolo Giuseppe CAPPELLETTI, Gabriele NAVARRO
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Patent number: 10910558Abstract: A phase-change memory cell includes, in at least a first portion, a stack of at least one germanium layer covered by at least one layer made of a first alloy of germanium, antimony, and tellurium. In a programmed state, resulting from heating a portion of the stack to a sufficient temperature, portions of layers of germanium and of the first alloy form a second alloy made up of germanium, antimony, and tellurium, where the second alloy has a higher germanium concentration than the first alloy.Type: GrantFiled: August 6, 2019Date of Patent: February 2, 2021Assignees: STMicroelectronics S.r.l., Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Paolo Giuseppe Cappelletti, Gabriele Navarro
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Publication number: 20200381618Abstract: A phase-change memory cell is formed by a heater, a crystalline layer disposed above the heater, and an insulating region surrounding sidewalls of the crystalline layer. The phase-change memory cell supports programming with a least three distinct data levels based on a selective amorphization of the crystalline layer.Type: ApplicationFiled: May 26, 2020Publication date: December 3, 2020Applicant: STMicroelectronics S.r.l.Inventor: Paolo Giuseppe CAPPELLETTI
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Publication number: 20200052199Abstract: A phase-change memory cell includes, in at least a first portion, a stack of at least one germanium layer covered by at least one layer made of a first alloy of germanium, antimony, and tellurium In a programmed state, resulting from heating a portion of the stack to a sufficient temperature, portions of layers of germanium and of the first alloy form a second alloy made up of germanium, antimony, and tellurium, where the second alloy has a higher germanium concentration than the first alloy.Type: ApplicationFiled: August 6, 2019Publication date: February 13, 2020Applicants: STMicroelectronics S.r.l., Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Paolo Giuseppe CAPPELLETTI, Gabriele NAVARRO
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Publication number: 20200052198Abstract: A phase-change memory cell includes, in at least a first portion, a stack of at least one germanium layer covered by at least one layer made of a first alloy of germanium, antimony, and tellurium. In a programmed state, resulting from heating a portion of the stack to a sufficient temperature, portions of layers of germanium and of the first alloy form a second alloy made up of germanium, antimony, and tellurium, where the second alloy has a higher germanium concentration than the first alloy.Type: ApplicationFiled: August 6, 2019Publication date: February 13, 2020Applicants: STMicroelectronics S.r.l., Commissariat A L'Energie Atomique et aux Energies AlternativesInventors: Paolo Giuseppe CAPPELLETTI, Gabriele NAVARRO
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Patent number: 9577188Abstract: Some embodiments include semiconductor constructions having stacks containing electrically conductive material over dielectric material. Programmable material structures are directly against both the electrically conductive material and the dielectric material along sidewall surfaces of the stacks. Electrode material electrically coupled with the electrically conductive material of the stacks. Some embodiments include methods of forming memory cells in which a programmable material plate is formed along a sidewall surface of a stack containing electrically conductive material and dielectric material.Type: GrantFiled: September 14, 2015Date of Patent: February 21, 2017Assignee: Micron Technology, Inc.Inventors: Carmela Cupeta, Andrea Redaelli, Paolo Giuseppe Cappelletti
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Publication number: 20160056375Abstract: Some embodiments include semiconductor constructions having stacks containing electrically conductive material over dielectric material. Programmable material structures are directly against both the electrically conductive material and the dielectric material along sidewall surfaces of the stacks. Electrode material electrically coupled with the electrically conductive material of the stacks. Some embodiments include methods of forming memory cells in which a programmable material plate is formed along a sidewall surface of a stack containing electrically conductive material and dielectric material.Type: ApplicationFiled: September 14, 2015Publication date: February 25, 2016Inventors: Carmela Cupeta, Andrea Redaelli, Paolo Giuseppe Cappelletti
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Patent number: 9166159Abstract: Some embodiments include semiconductor constructions having stacks containing electrically conductive material over dielectric material. Programmable material structures are directly against both the electrically conductive material and the dielectric material along sidewall surfaces of the stacks. Electrode material electrically coupled with the electrically conductive material of the stacks. Some embodiments include methods of forming memory cells in which a programmable material plate is formed along a sidewall surface of a stack containing electrically conductive material and dielectric material.Type: GrantFiled: May 23, 2013Date of Patent: October 20, 2015Assignee: Micron Technology, Inc.Inventors: Carmela Cupeta, Andrea Redaelli, Paolo Giuseppe Cappelletti
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Publication number: 20140346429Abstract: Some embodiments include semiconductor constructions having stacks containing electrically conductive material over dielectric material. Programmable material structures are directly against both the electrically conductive material and the dielectric material along sidewall surfaces of the stacks. Electrode material electrically coupled with the electrically conductive material of the stacks. Some embodiments include methods of forming memory cells in which a programmable material plate is formed along a sidewall surface of a stack containing electrically conductive material and dielectric material.Type: ApplicationFiled: May 23, 2013Publication date: November 27, 2014Inventors: Carmela Cupeta, Andrea Redaelli, Paolo Giuseppe Cappelletti
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Patent number: 7560782Abstract: An integrated transistor device is formed in a chip of semiconductor material having an electrical-insulation region delimiting an active area accommodating a bipolar transistor of vertical type and a MOSFET of planar type, contiguous to one another. The active area accommodates a collector region; a bipolar base region contiguous to the collector region; an emitter region within the bipolar base region; a source region, arranged at a distance from the bipolar base region; a drain region; a channel region arranged between the source region and the drain region; and a well region. The drain region and the bipolar base region are contiguous and form a common base structure shared by the bipolar transistor and the MOSFET. Thereby, the integrated transistor device has a high input impedance and is capable of driving high currents, while only requiring a small integration area.Type: GrantFiled: November 27, 2006Date of Patent: July 14, 2009Inventors: Fabio Pellizzer, Paolo Giuseppe Cappelletti
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Patent number: 7320904Abstract: A method for manufacturing electrically non-active structures for an electronic circuit integrated on a semiconductor substrate is provided, with the electronic circuit including first and second electrically active structures. The method includes inserting the electrically non-active structures in the electronic circuit to make uniform a surface above the semiconductor substrate. The inserting includes identifying, among the electrically non-active structures, a first group of electrically non-active structures to be adjacent the first and second electrically active structures, and identifying, among the electrically non-active structures, a second group of electrically non-active structures not adjacent to the first and second electrically active structures. The method further includes defining, on the semiconductor substrate, the first and second groups of electrically non-active structures through different photolithographic steps.Type: GrantFiled: January 19, 2006Date of Patent: January 22, 2008Assignee: STMicroelectronics S.r.l.Inventors: Paolo Giuseppe Cappelletti, Alfonso Maurelli, Paola Zabberoni
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Patent number: 7001800Abstract: A method for manufacturing electrically non-active structures for an electronic circuit integrated on a semiconductor substrate is provided, with the electronic circuit including first and second electrically active structures. The method includes inserting the electrically non-active structures in the electronic circuit to make uniform a surface above the semiconductor substrate. The inserting includes identifying, among the electrically non-active structures, a first group of electrically non-active structures to be adjacent the first and second electrically active structures, and identifying, among the electrically non-active structures, a second group of electrically non-active structures not adjacent to the first and second electrically active structures. The method further includes defining, on the semiconductor substrate, the first and second groups of electrically non-active structures through different photolithographic steps.Type: GrantFiled: August 3, 2004Date of Patent: February 21, 2006Assignee: STMicroelectronics S.r.l.Inventors: Paolo Giuseppe Cappelletti, Alfonso Maurelli, Paola Zabberoni