Abstract: A process for the manufacturing of an integrated circuit including a low operating voltage, high-performance logic circuitry and an embedded memory device having a high operating voltage higher than the low operating voltage of the logic circuitry, providing for: on first portions of a semiconductor substrate, forming a first gate oxide layer for first transistors operating at the high operating voltage; on second portions of the semiconductor substrate, forming a second gate oxide layer for memory cells of the memory device; on the first and second gate oxide layers, forming from a first polysilicon layer gate electrodes for the first transistors, and floating-gate electrodes for the memory cells; forming over the floating-gate electrodes of the memory cells a dielectric layer; on third portions of the semiconductor substrate, forming a third gate oxide layer for second transistors operating at the low operating voltage; on the dielectric layer and on the third portions of the semiconductor substrate, formin

Abstract: A process for the manufacturing of an integrated circuit including a low operating voltage, high-performance logic circuitry and an embedded memory device having a high operating voltage higher than the low operating voltage of the logic circuitry, providing for: on first portions of a semiconductor substrate, forming a first gate oxide layer for first transistors operating at the high operating voltage; on second portions of the semiconductor substrate, forming a second gate oxide layer for memory cells of the memory device; on the first and second gate oxide layers, forming from a first polysilicon layer gate electrodes for the first transistors, and floating-gate electrodes for the memory cells; forming over the floating-gate electrodes of the memory cells a dielectric layer; on third portions of the semiconductor substrate, forming a third gate oxide layer for second transistors operating at the low operating voltage; on the dielectric layer and on the third portions of the semiconductor substrate, formin

Abstract: A process for the manufacturing of an integrated circuit including a low operating voltage, high-performance logic circuitry and an embedded memory device having a high operating voltage higher than the low operating voltage of the logic circuitry, providing for: on first portions of a semiconductor substrate, forming a first gate oxide layer for first transistors operating at the high operating voltage; on second portions of the semiconductor substrate, forming a second gate oxide layer for memory cells of the memory device; on the first and second gate oxide layers, forming from a first polysilicon layer gate electrodes for the first transistors, and floating-gate electrodes for the memory cells; forming over the floating-gate electrodes of the memory cells a dielectric layer; on third portions of the semiconductor substrate, forming a third gate oxide layer for second transistors operating at the low operating voltage; on the dielectric layer and on the third portions of the semiconductor substrate, formin

Abstract: A process for simultaneously fabricating memory cells, transistors, and diodes for protecting the tunnel oxide layer of the cells, using the DPCC process wherein the first polysilicon layer is not removed from the transistor area, and the gate regions of the transistors are formed by shorted first and second polysilicon layers. To form the diodes, the polyl layer is removed from the active areas in which the diodes are to be formed, using the same mask employed for shaping polyi; the interpoly dielectric layer and the gate oxide layer are removed from the active areas of the diodes, using the same mask employed for removing the dielectric layer from the transistor area; a second polysilicon layer is deposited directly on to the active areas of the diodes; and the poly2 doping ions penetrate the active areas to form N+ regions which, together with the substrate, constitute the protection diodes.

Abstract: A method employing a test structure identical to the memory array whose gate oxide quality is to be determined, except for the fact that the cells are connected electrically parallel to one another. The test structure is so stressed electrically as to extract electrons from the floating gate of the defective-gate-oxide cells and so modify the characteristic of the cell while leaving the charge of the non-defective cells unchanged. In this way, only the threshold of the defective cells is altered. A sub-threshold voltage is then applied to the test structure, and the drain current through the cells, which is related to the presence of at least one defective cell in the structure, is measured. Measurement and analysis of the current-voltage characteristic provides for determining the number of defective cells. The method is suitable for in-line quality control of the gate oxide of EPROM, EEPROM and flash-EEPROM memories.

Abstract: A method employing a test structure identical to the memory array whose gate oxide or interpoly dielectric quality is to be determined, except for the fact that the cells are connected electrically parallel to one another. The test structure is subjected to electrical stress of such a value and polarity as to extract electrons from the floating gate of the defective-gate-oxide or defective-interpoly-dielectric cells and so modify the characteristic of the cell while leaving the charge of the non-defective cells unchanged. In this way, only the threshold of the defective cells is altered. A subthreshold voltage is then applied to the test structure, and the drain current through the cells, which is related to the presence of at least one defective cell in the structure, is measured. Measurement and analysis of the current-voltage characteristic provides for determining the number of defective cells.