Abstract: A method and system for implementing error correcting code using a product code decoder. The method and system receive a product code, wherein the product code is a matrix of row and column component codes, generate a plurality of row syndromes column syndromes from the received product code, store the plurality of row syndromes in a row syndrome queue, store the plurality of column syndromes in a column syndrome queue, the column and row syndrome queue to support the plurality of modes of operation corresponding to the plurality of phases of decoding the product code, correct the plurality of row syndromes and columns syndromes in the row and column syndrome queues based on errors detected in respective row and column syndromes and errors detecting in overlapping syndromes, and correct the product code in a codeword buffer at locations corresponding to corrections in the plurality of row syndromes and the plurality of column syndromes.

Abstract: A method and system for implementing error correcting code using a product code decoder. The method and system receive a product code, wherein the product code is a matrix of row and column component codes, generate a plurality of row syndromes column syndromes from the received product code, store the plurality of row syndromes in a row syndrome queue, store the plurality of column syndromes in a column syndrome queue, the column and row syndrome queue to support the plurality of modes of operation corresponding to the plurality of phases of decoding the product code, correct the plurality of row syndromes and columns syndromes in the row and column syndrome queues based on errors detected in respective row and column syndromes and errors detecting in overlapping syndromes, and correct the product code in a codeword buffer at locations corresponding to corrections in the plurality of row syndromes and the plurality of column syndromes.

Abstract: Apparatuses and methods for performing an error correction code (ECC) operation are provided. One example method can include encoding data by including parity data for a number of cross-over bits, wherein the number of cross-over bits are bits located at intersections of column codewords and row codewords.

Abstract: A first data stored at a first portion of a memory cell and a second data stored at a second portion of the memory cell are identified. A first error rate associated with first data stored at the first portion of the memory cell is determined. The first error rate is adjusted to exceed a second error rate associated with the second data stored at the second portion of the memory cell. A determination is made as to whether the first error rate exceeds a threshold. The second data stored at the second portion of the memory cell is provided for use in an error correction operation in response to determining that the first error rate exceeds the threshold.

Abstract: Apparatuses and methods for performing an error correction code (ECC) operation are provided. One example method can include performing a first error code correction (ECC) operation on a portion of data, performing a second ECC operation on the portion of data in response to the first ECC operation failing, and performing a third ECC operation on the portion of data in response to the second ECC operation failing.

Abstract: A temperature related to a memory device is identified. It is determined whether the temperature related to the memory device satisfies a threshold temperature condition. Responsive to detecting that the temperature related to the memory device satisfies the threshold temperature condition, a parameter for a programming operation is adjusted from a first value to a second value to store data at the memory device.

Abstract: Methods and apparatuses for generating probabilistic information for error correction using current integration are disclosed. An example method comprises sensing a first plurality of memory cells based on a first sense threshold, responsive to sensing the first plurality of cells, associating a first set of probabilistic information with the first plurality of memory cells, sensing a second plurality of memory cells based on a second sense threshold, responsive to sensing the second plurality of memory cells, associating a second set of probabilistic information with the second plurality of memory cells, and performing an error correction operation on the first and second pluralities of memory cells based, at least in part, on the first and second values.

Abstract: The present disclosure includes apparatuses and methods for monitoring error correction operations performed in memory. A number of embodiments include a memory and circuitry configured to determine a quantity of erroneous data corrected during an error correction operation performed on soft data associated with a sensed data state of a number of memory cells of the memory, determine a quality of soft information associated with the erroneous data corrected during the error correction operation performed on the soft data, and determine whether to take a corrective action on the sensed data based on the quantity of the erroneous data corrected during the error correction operation and the quality of the soft information associated with the erroneous data corrected during the error correction operation.

Abstract: Apparatuses and methods for performing an error correction code (ECC) operation are provided. One example method can include performing a first error code correction (ECC) operation on a portion of data, performing a second ECC operation on the portion of data in response to the first ECC operation failing, and performing a third ECC operation on the portion of data in response to the second ECC operation failing.

Abstract: One example of layer-by-layer error correction can include iteratively error correcting the codeword on a layer-by-layer basis with the first error correction circuit in a first mode and determining on the layer-by-layer basis whether a number of parity errors in a particular layer is less than a threshold number of parity errors. The codeword can be transferred to a second error correction circuit when the number of parity errors is less than the threshold number of parity errors. The codeword can be iteratively error corrected with the first error correction circuit in a second mode when the number of parity errors is at least the threshold number of parity errors. The threshold number of parity errors can be at least partially based on an adjustable code rate of the first error correction circuit or the second error correction circuit.

Abstract: Apparatuses and methods for performing an error correction code (ECC) operation are provided. One example method can include encoding data by including parity data for a number of cross-over bits, wherein the number of cross-over bits are bits located at intersections of column codewords and row codewords.

Abstract: The present disclosure includes apparatuses and methods related to stopping criteria for layered iterative error correction. A number of methods can include receiving a codeword with an error correction circuit, iteratively error correcting the codeword with the error correction circuit including parity checking the codeword on a layer-by-layer basis and updating the codeword after each layer. Methods can include stopping the iterative error correction in response to a parity check being correct for a particular layer.

Abstract: Methods and apparatuses for determining likelihood of erroneous data bits stored in a plurality of memory cells. A sense circuit to perform a coarse sense operation to detect first memory cells of the plurality of memory cells that stored charge sufficiently above a transition voltage threshold where the first memory cells are unlikely to be erroneous. The sense circuit further performs a fine sense operation to sense second memory cells of the plurality of memory cells having stored charge near the transition voltage between adjacent logic states. The first memory cells remain unsensed during the fine sense operation. The second memory cells detected during the fine sense operation may have an increased likelihood of being erroneous. Responsive to a number of sensed second memory cells near the transition voltage exceeding a threshold, additional sensing operations are performed by the sense circuit.

Abstract: Methods and apparatuses for determining likelihood of erroneous data bits stored in a plurality of memory cells. A sense circuit to perform a coarse sense operation to detect first memory cells of the plurality of memory cells that stored charge sufficiently above a transition voltage threshold where the first memory cells are unlikely to be erroneous. The sense circuit further performs a fine sense operation to sense second memory cells of the plurality of memory cells having stored charge near the transition voltage between adjacent logic states. The first memory cells remain unsensed during the fine sense operation. The second memory cells detected during the fine sense operation may have an increased likelihood of being erroneous. Responsive to a number of sensed second memory cells near the transition voltage exceeding a threshold, additional sensing operations are performed by the sense circuit.

Abstract: An apparatus is provided. The apparatus comprises a first syndrome computation circuit configured to receive a codeword having a plurality of rows and a plurality of columns and further configured to compute a first syndrome for at least a portion of a first component codeword of the codeword. The apparatus further comprises a second syndrome computation circuit configured to receive the codeword and to compute a second syndrome for at least a portion of a second component codeword of the codeword. The apparatus further comprises a bit correction circuit configured to correct one or more erroneous bits in the codeword based, at least in part, on at least one of the first and second syndrome, wherein the first and second component codewords span two or more rows and two or more columns of the codeword.

Abstract: The present disclosure includes apparatuses and methods related to stopping criteria for layered iterative error correction. A number of methods can include receiving a codeword with an error correction circuit, iteratively error correcting the codeword with the error correction circuit including parity checking the codeword on a layer-by-layer basis and updating the codeword after each layer. Methods can include stopping the iterative error correction in response to a parity check being correct for a particular layer.

Abstract: The present disclosure includes apparatuses and methods for estimating an error rate associated with memory. A number of embodiments include sensing data stored in a memory, performing an error detection operation on the sensed data, determining a quantity of parity violations associated with the error detection operation, and estimating an error rate associated with the memory based on the determined quantity of parity violations.

Abstract: An apparatus is provided. The apparatus comprises a first syndrome computation circuit configured to receive a codeword having a plurality of rows and a plurality of columns and further configured to compute a first syndrome for at least a portion of a first component codeword of the codeword. The apparatus further comprises a second syndrome computation circuit configured to receive the codeword and to compute a second syndrome for at least a portion of a second component codeword of the codeword. The apparatus further comprises a bit correction circuit configured to correct one or more erroneous bits in the codeword based, at least in part, on at least one of the first and second syndrome, wherein the first and second component codewords span two or more rows and two or more columns of the codeword.

Abstract: Apparatuses and methods for performing an error correction code (ECC) operation are provided. One example method can include encoding data by including parity data for a number of cross-over bits, wherein the number of cross-over bits are bits located at intersections of column codewords and row codewords.

Abstract: The present disclosure includes apparatuses and methods related to memory cell state in a valley between adjacent data states. A number of methods can include determining whether a state of a memory cell is in a valley between adjacent distributions of states associated with respective data states. The method can also include transmitting a signal indicative of a data state of the memory cell and whether the state of the memory cell is in the valley.