Abstract: Implementations of the present disclosure include actions of receiving image data of an image capturing a scene, receiving data describing one or more entities determined from the scene, the one or more entities being determined from the scene, determining one or more actions based on the one or more entities, each action being provided at least partly based on search results from searching the one or more entities, and providing instructions to display an action interface comprising one or more action elements, each action element being to induce execution of a respective action, the action interface being displayed in a viewfinder

Abstract: Implementations of the present disclosure include actions of receiving image data of an image capturing a scene, receiving data describing one or more entities determined from the scene, the one or more entities being determined from the scene, determining one or more actions based on the one or more entities, each action being provided at least partly based on search results from searching the one or more entities, and providing instructions to display an action interface comprising one or more action elements, each action element being to induce execution of a respective action, the action interface being displayed in a viewfinder.

Abstract: A user of a user device with a first account with an online service selects a contact to invite to join the online service. A server receives the selected contact to invite from the user device, and in response to receiving the selected contact, generates a second account for the selected contact. The second account includes a plurality of fields, one or more of which are populated with contact information of the selected contact. A link to the second account is generated and provided in an invitation for the selected contact to activate the second account with the online service.

Abstract: Chip structures and fabrication methods for forming such chip structures. A first device structure has a structural feature comprised of a first dielectric material and a second device structure has a structural feature comprised of a second dielectric material. A semiconductor layer has a first section adjacent to the structural feature of the first device structure and a second section adjacent to the structural feature of the second device structure. The first section of the semiconductor layer has a popped relationship relative to the structural feature comprised of the first dielectric material. The second section of the semiconductor layer includes a portion that has a pinned relationship relative to a portion of the structural feature comprised of the second dielectric material.

Abstract: A semiconductor device and a method for manufacturing the device. The method includes: depositing a first dielectric layer on a semiconductor device; forming a plurality of first trenches through the first dielectric layer; depositing an insulating fill in the plurality of first trenches; planarizing the plurality of first trenches; forming a first gate contact between the plurality of first trenches; depositing a first contact fill in the first gate contact; planarizing the first gate contact; depositing a second dielectric layer on the device; forming a plurality of second trenches through the first and second dielectric layers; depositing a conductive fill in the plurality of second trenches; planarizing the plurality of second trenches; forming a second gate contact where the second gate contact is in contact with the first gate contact; depositing a second contact fill in the second gate contact; and planarizing the second gate contact.

Abstract: A method for decoding a compressed video data sequence containing one or more coded pixel blocks. The compressed video sequence is buffered. Prediction information for each of the coded pixel blocks is reviewed. One or more groups of coded pixel blocks are formed based on the reviewed prediction information such that the coded pixel blocks within a given group have similar prediction dependencies and/or at least do not depend on a reconstructed pixel within a group of received pixel blocks to enable parallel decoding. The formed groups are scheduled for processing and subsequently decoded to produce a decoded video data sequence.

Abstract: A hybrid compression method for compressing images is provided. The method identifies a first set of image components to be compressed by a lossy compression format and a second set of image components to be compressed by a lossless compression format. The method then encodes the first set of image components according to the lossy compression format and encodes the second set of image components according to the lossless compression format. The method then generates a compressed structure that includes the lossy-compressed first set of image components and the lossless-compressed second set of image components.

Abstract: Examples described herein include methods and systems for adjusting images which may be captured, for example, by a wearable camera. The wearable camera may be devoid of a viewfinder. Accordingly, it may be desirable to adjust images captured by the wearable camera prior to display to a user. Image adjustment techniques may employ physical wedges, calibration techniques, and/or machine learning techniques as described herein.

Abstract: Chip structures and fabrication methods for forming such chip structures. A first device structure has a structural feature comprised of a first dielectric material and a second device structure has a structural feature comprised of a second dielectric material. A semiconductor layer has a first section adjacent to the structural feature of the first device structure and a second section adjacent to the structural feature of the second device structure. The first section of the semiconductor layer has a popped relationship relative to the structural feature comprised of the first dielectric material. The second section of the semiconductor layer includes a portion that has a pinned relationship relative to a portion of the structural feature comprised of the second dielectric material.

Abstract: A performance optimized CMOS FET structure and methods of manufacture are disclosed. The method includes forming source and drain regions for a first type device and a second type device. The method further includes lowering the source and drain regions for the first type device, while protecting the source and drain regions for the second type device. The method further includes performing silicide processes to form silicide regions on the lowered source and drain regions for the first type device and the source and drain regions for the second type device.

Abstract: A performance optimized CMOS FET structure and methods of manufacture are disclosed. The method includes forming source and drain regions for a first type device and a second type device. The method further includes lowering the source and drain regions for the first type device, while protecting the source and drain regions for the second type device. The method further includes performing silicide processes to form silicide regions on the lowered source and drain regions for the first type device and the source and drain regions for the second type device.

Abstract: The disclosure relates to semiconductor structures and, more particularly, to one or more devices with an engineered layer for modulating voltage threshold (Vt) and methods of manufacture. The method includes finding correlation of thickness of a buffer layer to out-diffusion of dopant into extension regions during annealing of a doped layer formed on the buffer layer. The method further includes determining a predetermined thickness of the buffer layer to adjust device performance characteristics based on the correlation of thickness of the buffer layer to the out-diffusion. The method further includes forming the buffer layer adjacent to gate structures to the predetermined thickness.

Abstract: A method for decoding a compressed video data sequence containing one or more coded pixel blocks. The compressed video sequence is buffered. Prediction information for each of the coded pixel blocks is reviewed. One or more groups of coded pixel blocks are formed based on the reviewed prediction information such that the coded pixel blocks within a given group have similar prediction dependencies and/or at least do not depend on a reconstructed pixel within a group of received pixel blocks to enable parallel decoding. The formed groups are scheduled for processing and subsequently decoded to produce a decoded video data sequence.

Abstract: Implementations of the present disclosure include actions of receiving image data of an image capturing a scene, receiving data describing one or more entities determined from the scene, the one or more entities being determined from the scene, determining one or more actions based on the one or more entities, each action being provided at least partly based on search results from searching the one or more entities, and providing instructions to display an action interface comprising one or more action elements, each action element being to induce execution of a respective action, the action interface being displayed in a viewfinder

Abstract: A system, method and computer program product for implementing a quiescent current leakage specific model into semiconductor device design and circuit design flows. The leakage model covers all device geometries with wide temperature and voltage ranges and, without the need for stacking factor calculations nor spread sheet based IDDQ calculations. The leakage model for IDDQ calculation incorporates further parasitic and proximity effects. The leakage model implements leakage calculations at different levels of testing, e.g., from a single device to a full chip design, and are integrated within one single model. The leakage model implements leakage calculations at different levels of testing with the leverage of a single switch setting. The implementation is via a hardware definition language code or object oriented code that can be compiled and operated using a netlist of interest, e.g., for conducting a performance analysis.

Abstract: The disclosure relates to semiconductor structures and, more particularly, to one or more devices with an engineered layer for modulating voltage threshold (Vt) and methods of manufacture. The method includes finding correlation of thickness of a buffer layer to out-diffusion of dopant into extension regions during annealing of a doped layer formed on the buffer layer. The method further includes determining a predetermined thickness of the buffer layer to adjust device performance characteristics based on the correlation of thickness of the buffer layer to the out-diffusion. The method further includes forming the buffer layer adjacent to gate structures to the predetermined thickness.

Abstract: Implementations of the present disclosure include actions of receiving image data, the image data being provided from a camera and corresponding to a scene viewed by the camera, receiving one or more annotations, the one or more annotations being provided based on one or more entities determined from the scene, each annotation being associated with at least one entity, determining one or more actions based on the one or more annotations, and providing instructions to display an action interface including one or more action elements, each action element being selectable to induce execution of a respective action, the action interface being displayed in a viewfinder.

Abstract: Silicided nanowires as nanobridges in Josephson junctions. A superconducting silicided nanowire is used as a weak-link bridge in a Josephson junction, and a fabrication process is employed to produce silicided nanowires that includes patterning two junction banks and a rough nanowire from a silicon substrate, reshaping the nanowire through hydrogen annealing, and siliciding the nanowire by introduction of a metal into the nanowire structure.