Patents by Inventor Paul Chang
Paul Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150134522Abstract: A system, apparatus, and computer-readable storage medium configured to indicate an elevated status of a customer via an enhanced authorization message.Type: ApplicationFiled: November 8, 2013Publication date: May 14, 2015Applicant: MASTERCARD INTERNATIONAL INCORPORATEDInventors: James Carrington, Matthew Sordi, Paul Chang
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Patent number: 9024355Abstract: Fin-defining mask structures are formed over a semiconductor material layer having a first semiconductor material and a disposable gate structure is formed thereupon. A gate spacer is formed around the disposable gate structure and physically exposed portions of the fin-defining mask structures are subsequently removed. The semiconductor material layer is recessed employing the disposable gate structure and the gate spacer as an etch mask to form recessed semiconductor material portions. Embedded planar source/drain stressors are formed on the recessed semiconductor material portions by selective deposition of a second semiconductor material having a different lattice constant than the first semiconductor material. After formation of a planarization dielectric layer, the disposable gate structure is removed. A plurality of semiconductor fins are formed employing the fin-defining mask structures as an etch mask. A replacement gate structure is formed on the plurality of semiconductor fins.Type: GrantFiled: May 30, 2012Date of Patent: May 5, 2015Assignee: International Business Machines CorporationInventors: Josephine B. Chang, Paul Chang, Michael A. Guillorn, Jeffrey W. Sleight
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Patent number: 9000530Abstract: A memory device includes a first plurality of semiconductor nanowires tethered between landing pads and suspended over a substrate. A first gate electrode surrounds each of the first plurality of semiconductor nanowires, making them gate-all-around (GAA) semiconductor nanowires. First, second, and third field effect transistors (FETs) are formed by the first plurality of semiconductor nanowires. The memory device also includes a second plurality of semiconductor nanowires tethered between landing pads and suspended over the substrate. A second gate electrode surrounds each of the second plurality of semiconductor nanowires, making them GAA semiconductor nanowires. Fourth, fifth, and sixth FETs are formed by the second plurality of semiconductor nanowires.Type: GrantFiled: April 23, 2013Date of Patent: April 7, 2015Assignee: International Business Machines CorporationInventors: Karthik Balakrishnan, Josephine B. Chang, Paul Chang, Michael A. Guillorn
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Patent number: 8997028Abstract: Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.Type: GrantFiled: April 22, 2013Date of Patent: March 31, 2015Assignee: Mentor Graphics CorporationInventors: James A. Culp, Paul Chang, Dureseti Chidambarrao, Praveen Elakkumanan, Jason Hibbeler, Anda C. Mocuta
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Publication number: 20150084096Abstract: A faceted intrinsic buffer semiconductor material is deposited on sidewalls of a source trench and a drain trench by selective epitaxy. A facet adjoins each edge at which an outer sidewall of a gate spacer adjoins a sidewall of the source trench or the drain trench. A doped semiconductor material is subsequently deposited to fill the source trench and the drain trench. The doped semiconductor material can be deposited such that the facets of the intrinsic buffer semiconductor material are extended and inner sidewalls of the deposited doped semiconductor material merges in each of the source trench and the drain trench. The doped semiconductor material can subsequently grow upward. Faceted intrinsic buffer semiconductor material portions allow greater outdiffusion of dopants near faceted corners while suppressing diffusion of dopants in regions of uniform width, thereby suppressing short channel effects.Type: ApplicationFiled: October 7, 2014Publication date: March 26, 2015Inventors: Bhupesh Chandra, Paul Chang, Gregory G. Freeman, Dechao Guo, Judson R. Holt, Arvind Kumar, Timothy J. McArdle, Shreesh Narasimha, Viorel Ontalus, Sangameshwar Saudari, Christopher D. Sheraw, Matthew W. Stoker
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Patent number: 8981478Abstract: Semiconductor devices and methods that include forming a fin field effect transistor by defining a fin hardmask on a semiconductor layer, forming a dummy structure over the fin hardmask to establish a planar area on the semiconductor layer, removing a portion of the fin hardmask that extends beyond the dummy structure, etching a semiconductor layer adjacent to the dummy structure to produce recessed source and drain regions, removing the dummy structure, etching the semiconductor layer in the planar area to produce fins, and forming a gate stack over the fins.Type: GrantFiled: September 12, 2012Date of Patent: March 17, 2015Assignee: International Business Machines CorporationInventors: Josephine B. Chang, Paul Chang, Michael A. Guillorn, Chung-Hsun Lin, Jeffrey W. Sleight
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Patent number: 8949080Abstract: A method of designing an integrated circuit includes performing a pre-layout simulation of the integrated circuit. The pre-layout simulation is performed using a netlist generated from a process design kit (PDK) file. The PDK file includes a plurality of device model cards that are assigned to plurality of devices. The plurality of devices include a first device having at least one parasitic diode that is associated with at least one isolation well, the PDK file including information of the at least one parasitic diode. A design layout of the integrated circuit corresponding to a result of the pre-layout simulation is generated.Type: GrantFiled: August 25, 2010Date of Patent: February 3, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kuo-Tsai Li, Paul Chang, Andy Chang
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Patent number: 8940595Abstract: A faceted intrinsic buffer semiconductor material is deposited on sidewalls of a source trench and a drain trench by selective epitaxy. A facet adjoins each edge at which an outer sidewall of a gate spacer adjoins a sidewall of the source trench or the drain trench. A doped semiconductor material is subsequently deposited to fill the source trench and the drain trench. The doped semiconductor material can be deposited such that the facets of the intrinsic buffer semiconductor material are extended and inner sidewalls of the deposited doped semiconductor material merges in each of the source trench and the drain trench. The doped semiconductor material can subsequently grow upward. Faceted intrinsic buffer semiconductor material portions allow greater outdiffusion of dopants near faceted corners while suppressing diffusion of dopants in regions of uniform width, thereby suppressing short channel effects.Type: GrantFiled: March 15, 2013Date of Patent: January 27, 2015Assignee: International Business Machines CorporationInventors: Bhupesh Chandra, Paul Chang, Gregory G. Freeman, Dechao Guo, Judson R. Holt, Arvind Kumar, Timothy J. McArdle, Shreesh Narasimha, Viorel Ontalus, Sangameshwar Rao Saudari, Christopher D. Sheraw, Matthew W. Stoker
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Patent number: 8900959Abstract: A gate-first processing scheme for forming a nanomesh field effect transistor is provided. An alternating stack of two different semiconductor materials is patterned to include two pad regions and nanowire regions. A semiconductor material is laterally etched selective to another semiconductor material to form a nanomesh including suspended semiconductor nanowires. A stack of a gate dielectric, a gate electrode, and a gate cap dielectric is formed over the nanomesh. A dielectric spacer is formed around the gate electrode. An isotropic etch is employed to remove dielectric materials that are formed in lateral recesses of the patterned alternating stack. A selective epitaxy process can be employed to form a source region and a drain region.Type: GrantFiled: March 12, 2013Date of Patent: December 2, 2014Assignee: International Business Machines CorporationInventors: Josephine B. Chang, Paul Chang, Isaac Lauer, Jeffrey W. Sleight
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Publication number: 20140348857Abstract: The present invention relates to methods for treating endoplasmic reticulum (ER) stress-related conditions (e.g., cancer, protein folding/misfolding disease, diabetes mellitus) and for identifying compounds for treating ER stress-related conditions in a subject (e.g., a human). The invention also provides methods for diagnosing an ER stress-related condition in a subject and kits for the treatment of same.Type: ApplicationFiled: October 26, 2012Publication date: November 27, 2014Applicant: MASSACHUSETTS INSTITUTE OF TECHNOLOGYInventors: Paul Chang, Miri Jwa, Sejal Kamlesh Vyas
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Publication number: 20140315363Abstract: A memory device includes a first plurality of semiconductor nanowires tethered between landing pads and suspended over a substrate. A first gate electrode surrounds each of the first plurality of semiconductor nanowires, making them gate-all-around, (GAA) semiconductor nanowires. First, second, and third field effect transistors (FETs) are formed by the first plurality of semiconductor nanowires. The memory device also includes a second plurality of semiconductor nanowires tethered between landing pads and suspended over the substrate. A second gate electrode surrounds each of the second plurality of semiconductor nanowires, making them GAA semiconductor nanowires. Fourth, fifth, and sixth FETs are formed by the second plurality of semiconductor nanowires.Type: ApplicationFiled: August 20, 2013Publication date: October 23, 2014Applicant: International Business Machines CorporationInventors: Karthik Balakrishnan, Josephine B. Chang, Paul Chang, Michael A. Guillorn
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Patent number: 8845247Abstract: A milling machine has a base, a work platform mounted movably on the base, and a ruler mounted on the work platform. The work platform is movable relative to a base axis. The thermal compensation system includes a sensor and a control unit. The sensor is configured to be mounted on the base for sensing a position of each of the work platform and the ruler relative to the base axis. The control unit is coupled to the sensor, and determines a work platform displacement and a ruler displacement according to the positions sensed by the sensor. The control unit further calculates a compensation value based on the work platform displacement and the ruler displacement. The control unit is configured to correct the position of the work platform relative to the base axis according to the compensation value.Type: GrantFiled: June 28, 2011Date of Patent: September 30, 2014Assignees: Buffalo Machinery Company Limited, The Department of Electrical Engineering, National Chang-Hua University of EducationInventors: Ching-Wei Wu, Ying-Shing Shiao, Chia-Hui Tang, Yu-Che Wang, Paul Chang
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Publication number: 20140264558Abstract: A faceted intrinsic buffer semiconductor material is deposited on sidewalls of a source trench and a drain trench by selective epitaxy. A facet adjoins each edge at which an outer sidewall of a gate spacer adjoins a sidewall of the source trench or the drain trench. A doped semiconductor material is subsequently deposited to fill the source trench and the drain trench. The doped semiconductor material can be deposited such that the facets of the intrinsic buffer semiconductor material are extended and inner sidewalls of the deposited doped semiconductor material merges in each of the source trench and the drain trench. The doped semiconductor material can subsequently grow upward. Faceted intrinsic buffer semiconductor material portions allow greater outdiffusion of dopants near faceted corners while suppressing diffusion of dopants in regions of uniform width, thereby suppressing short channel effects.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bhupesh Chandra, Paul Chang, Gregory G. Freeman, Dechao Guo, Judson R. Holt, Arvind Kumar, Timothy J. McArdle, Shreesh Narasimha, Viorel Ontalus, Sangameshwar Rao Saudari, Christopher D. Sheraw, Matthew W. Stoker
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Publication number: 20140264276Abstract: A gate-first processing scheme for forming a nanomesh field effect transistor is provided. An alternating stack of two different semiconductor materials is patterned to include two pad regions and nanowire regions. A semiconductor material is laterally etched selective to another semiconductor material to form a nanomesh including suspended semiconductor nanowires. A stack of a gate dielectric, a gate electrode, and a gate cap dielectric is formed over the nanomesh. A dielectric spacer is formed around the gate electrode. An isotropic etch is employed to remove dielectric materials that are formed in lateral recesses of the patterned alternating stack. A selective epitaxy process can be employed to form a source region and a drain region.Type: ApplicationFiled: March 12, 2013Publication date: September 18, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Josephine B. Chang, Paul Chang, Isaac Lauer, Jeffrey W. Sleight
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Patent number: 8836087Abstract: Disposable gate structures are formed on a semiconductor substrate. A planarization dielectric layer is deposited over the disposable gate structures and planarized to provide a top surface that is coplanar with top surface of the disposable gate structures. The planarization dielectric layer at this point includes gap-fill keyholes between narrowly spaced disposable gate structures. A printable dielectric layer is deposited over the planarization dielectric layer to fill the gap-fill keyholes. Areas of the printable dielectric layer over the gap-fill keyholes are illuminated with radiation that cross-links cross-linkable bonds in the material of the printable dielectric layer. Non-crosslinked portions of the printable dielectric layer are subsequently removed selective to crosslinked portions of the printable dielectric layer, which fills at least the upper portion of each gate-fill keyhole. The disposable gate structures are removed to form gate cavities.Type: GrantFiled: January 17, 2014Date of Patent: September 16, 2014Assignee: International Business Machines CorporationInventors: Paul Chang, Josephine B. Chang, Michael A. Guillorn, Jeffrey W. Sleight
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Patent number: 8796742Abstract: An alternating stack of two different semiconductor materials is patterned to include two pad regions and nanowire regions. A semiconductor material is laterally etched selective to another semiconductor material to form a nanomesh including suspended semiconductor nanowires. Gate dielectrics, a gate electrode, and a gate cap dielectric are formed over the nanomesh. A dielectric spacer is formed around the gate electrode. The semiconductor materials in the two pad regions and physically exposed portions of the nanomesh are removed employing the dielectric spacer and the gate cap dielectric as an etch mask. A source region and a drain region are epitaxially grown from end surfaces of the nanomesh.Type: GrantFiled: September 10, 2013Date of Patent: August 5, 2014Assignee: International Business Machines CorporationInventors: Josephine B. Chang, Paul Chang, Isaac Lauer, Jeffrey W. Sleight
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Patent number: 8785981Abstract: A gate-first processing scheme for forming a nanomesh field effect transistor is provided. An alternating stack of two different semiconductor materials is patterned to include two pad regions and nanowire regions. A semiconductor material is laterally etched selective to another semiconductor material to form a nanomesh including suspended semiconductor nanowires. A stack of a gate dielectric, a gate electrode, and a gate cap dielectric is formed over the nanomesh. A dielectric spacer is formed around the gate electrode. An isotropic etch is employed to remove dielectric materials that are formed in lateral recesses of the patterned alternating stack. A selective epitaxy process can be employed to form a source region and a drain region.Type: GrantFiled: September 10, 2013Date of Patent: July 22, 2014Assignee: International Business Machines CorporationInventors: Josephine B. Chang, Paul Chang, Isaac Lauer, Jeffrey W. Sleight
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Patent number: 8778768Abstract: An alternating stack of two different semiconductor materials is patterned to include two pad regions and nanowire regions. A semiconductor material is laterally etched selective to another semiconductor material to form a nanomesh including suspended semiconductor nanowires. Gate dielectrics, a gate electrode, and a gate cap dielectric are formed over the nanomesh. A dielectric spacer is formed around the gate electrode. The semiconductor materials in the two pad regions and physically exposed portions of the nanomesh are removed employing the dielectric spacer and the gate cap dielectric as an etch mask. A source region and a drain region are epitaxially grown from end surfaces of the nanomesh.Type: GrantFiled: March 12, 2013Date of Patent: July 15, 2014Assignee: International Business Machines CorporationInventors: Josephine B. Chang, Paul Chang, Issac Lauer, Jeffrey W. Sleight
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Patent number: 8779414Abstract: A disposable material layer is first deposited on a graphene layer or a carbon nanotube (CNT). The disposable material layer includes a material that is less inert than graphene or CNT so that a contiguous dielectric material layer can be deposited at a target dielectric thickness without pinholes therein. A gate stack is formed by patterning the contiguous dielectric material layer and a gate conductor layer deposited thereupon. The disposable material layer shields and protects the graphene layer or the CNT during formation of the gate stack. The disposable material layer is then removed by a selective etch, releasing a free-standing gate structure. The free-standing gate structure is collapsed onto the graphene layer or the CNT below at the end of the selective etch so that the bottom surface of the contiguous dielectric material layer contacts an upper surface of the graphene layer or the CNT.Type: GrantFiled: June 21, 2013Date of Patent: July 15, 2014Assignee: International Business Machines CorporationInventors: Josephine B. Chang, Paul Chang, Michael A. Guillorn, Philip S. Waggoner
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Publication number: 20140190405Abstract: A chemical vapor deposition reactor and a method of wafer processing are provided. The reactor can include a reaction chamber having an interior and an entry port for insertion and removal of substrates, a gas inlet manifold communicating with the interior of the chamber for admitting process gasses to form a deposit on substrates held within the interior, a shutter mounted to the chamber, and one or more cleaning elements mounted within the chamber. The shutter can be movable between (i) a run position in which the cleaning elements are remote from the exhaust channel and (ii) a cleaning position in which the one or more cleaning elements engage with the shutter so that the cleaning elements remove deposited particles from the shutter upon movement of the shutter to the cleaning position.Type: ApplicationFiled: January 8, 2013Publication date: July 10, 2014Applicant: VEECO INSTRUMENTS INC.Inventors: Chenghung Paul Chang, Keng Moy, Alexander I. Gurary