Patents by Inventor Paul G. Davis
Paul G. Davis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7870357Abstract: A method of operating a memory component that includes a memory core includes receiving, from external control lines, a write command that specifies a write operation. The write command is stored for a first time period after receiving the write command. After the first time period, the write operation is initiated in response to the write command. During the write operation, unmasked portions of received data are written to the memory core, where the unmasked portions of the data are bits of the data that are identified by received mask information as not being masked.Type: GrantFiled: September 30, 2008Date of Patent: January 11, 2011Assignee: Rambus Inc.Inventors: Paul G. Davis, Frederick A. Ware, Craig E. Hampel
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Publication number: 20100332719Abstract: In a method of controlling a memory device, the following is conveyed over a first set of interconnect resources: a first command that specifies activation of a row of memory cells; a second command that specifies a write operation, wherein write data is written to the row; a bit that specifies whether precharging occurs after the write data is written; and a code that specifies whether data mask information will be issued for the write operation. If the code specifies that the information will be issued, then the information, which specifies whether to selectively write portions of the write data, is conveyed over the first set of interconnect resources after conveying the code. The write data to be written in connection with the write operation is conveyed over a second set of interconnect resources that is separate from the first set of interconnect resources.Type: ApplicationFiled: September 3, 2010Publication date: December 30, 2010Inventors: Richard M. Barth, Frederick A. Ware, Donald C. Stark, Craig E. Hampel, Paul G. Davis, Abhijit M. Abhyankar, James A. Gasbarre, David Nguyen
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Patent number: 7861030Abstract: A method for providing field updates through the use of a memory emulation circuit with a content addressable memory (CAM) as the intelligent portion of the emulation circuit's arbiter. CAM circuit 200 is comprised of configurable memory and is initially unprogrammed. Address requests are passed straight through multiplexer 201 to Read Only Memory (ROM) 202. As a result the data in the data location in ROM 202 that corresponds to the requested address will be output to data bus 205. If data locations in ROM 202 become defective or contain data that needs to be upgraded the circuit implements a remapping of the data location. CAM circuit 200 is programmed with direct addresses to be replaced in ROM 202. The direct addresses are paired to emulation addresses of data locations in configurable memory 203. Upgraded or substitute data is programmed into the configurable memory 203 at the paired emulation address.Type: GrantFiled: March 5, 2008Date of Patent: December 28, 2010Assignee: Microchip Technology IncorporatedInventor: Paul G. Davis
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Patent number: 7793039Abstract: A semiconductor memory device includes a memory core, a first interface to receive write data from a first set of interconnect resources, and a second interface, separate from the first interface, to receive from a second set of interconnect resources a column address and a first code. The column address is associated with the write data and identifies a column of the memory core in which to store the write data. The first code indicates whether the write data is selectively masked by data mask information. If the first code indicates that the write data is selectively masked, the second interface is to receive data mask information specifying whether to selectively write portions of the write data to the memory core.Type: GrantFiled: January 6, 2009Date of Patent: September 7, 2010Assignee: Rambus Inc.Inventors: Richard M. Barth, Frederick A. Ware, Donald C. Stark, Craig E. Hampel, Paul G. Davis, Abhijit M. Abhyankar, James A. Gasbarro, David Nguyen
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Patent number: 7581121Abstract: A system comprising a storage location to store information representing a timing parameter pertaining to a random access memory device. An integrated circuit device generates a value that is representative of a period of time that elapses between the random access memory device exiting from a power down mode and a time at which the random access memory device is capable of receiving a command. The integrated circuit device generates the value from the information representing the timing parameter pertaining to the random access memory device.Type: GrantFiled: June 14, 2005Date of Patent: August 25, 2009Assignee: Rambus Inc.Inventors: Richard M. Barth, Ely K. Tsern, Craig E. Hampel, Frederick A. Ware, Todd W. Bystrom, Bradley A. May, Paul G. Davis
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Patent number: 7574616Abstract: A memory device including an array of memory cells, and a register circuit to store a value representative of a period of time to elapse before the memory device is ready to receive a command when recovering from a power down mode is provided in an embodiment. The command specifies an access to the array of memory cells. A delay lock loop circuit synchronizes data transfers using an external clock signal. The delay lock loop circuit reacquires synchronization with the external clock signal during the period of time.Type: GrantFiled: September 17, 2004Date of Patent: August 11, 2009Assignee: Rambus Inc.Inventors: Richard M. Barth, Ely K. Tsern, Craig E. Hampel, Frederick A. Ware, Todd W. Bystrom, Bradley A. May, Paul G. Davis
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Patent number: 7571330Abstract: A memory module comprises a memory device including a memory array to store data. An interface receives an instruction to exit a power down mode. A register stores a value representative of a period of time to elapse between exiting from the power down mode and a time at which the memory device is capable of receiving a command to access the data. A storage device stores a plurality of parameter information that pertains to the memory device. The value is based on at least a first parameter information of the plurality of parameter information.Type: GrantFiled: May 25, 2005Date of Patent: August 4, 2009Assignee: Rambus Inc.Inventors: Richard M. Barth, Ely K. Tsern, Craig E. Hampel, Frederick A. Ware, Todd W. Bystrom, Bradley A. May, Paul G. Davis
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Publication number: 20090129178Abstract: An integrated circuit memory device includes a memory core to store write data, a first set of interconnect resources to receive the write data, and a second set of interconnect resources to receive a write command associated with the write data. Information indicating whether mask information is included with the write command, wherein the mask information, when included in the write command, specifies whether to selectively write portions of the write data to the memory core.Type: ApplicationFiled: January 6, 2009Publication date: May 21, 2009Inventors: Richard M. Barth, Frederick A. Ware, Donald C. Stark, Craig E. Hampel, Paul G. Davis, Abhijit M. Abhyankar, James A. Gasbarro, David Nguyen
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Publication number: 20090119444Abstract: The present invention produces a low-cost reliable non-volatile memory with multiple write cycles. The memory circuit trades full configurability for increased reliability and decreased cost by providing a limited number of write or rewrite cycles utilizing an indirectly accessible register set that writes data into fully configurable memory. The circuit is useful for both providing upgrade capability to electronic computational systems and data robustness to logic storage systems. Less configurable non-volatile memory (NVM) block 201 is utilized in tandem with directly accessible fully configurable memory block 207. Arbiter 206 implements the redundant addressing that enables the multiple write cycle NVM functionality. Each block of less configurable memory contains an address segment 203 and a data segment 204. Address segment 203 refers to a specific cell in directly accessible memory 209.Type: ApplicationFiled: November 1, 2007Publication date: May 7, 2009Applicant: ZeroG Wireless, Inc., Delaware CorporationInventor: Paul G. Davis
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Patent number: 7496709Abstract: An integrated circuit memory device includes a memory core to store write data, a first set of interconnect resources to receive the write data, and a second set of interconnect resources to receive a write command associated with the write data. Information indicating whether mask information is included with the write command, wherein the mask information, when included in the write command, specifies whether to selectively write portions of the write data to the memory core.Type: GrantFiled: December 10, 2007Date of Patent: February 24, 2009Assignee: Rambus Inc.Inventors: Richard M. Barth, Frederick A. Ware, Donald C. Stark, Craig E. Hampel, Paul G. Davis, Abhijit M. Abhyankar, James A. Gasbarro, David Nguyen
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Publication number: 20090043957Abstract: A method for providing field updates through the use of a memory emulation circuit with a content addressable memory (CAM) as the intelligent portion of the emulation circuit's arbiter. CAM circuit 200 is comprised of configurable memory and is initially unprogrammed. Address requests are passed straight through multiplexer 201 to Read Only Memory (ROM) 202. As a result the data in the data location in ROM 202 that corresponds to the requested address will be output to data bus 205. If data locations in ROM 202 become defective or contain data that needs to be upgraded the circuit implements a remapping of the data location. CAM circuit 200 is programmed with direct addresses to be replaced in ROM 202. The direct addresses are paired to emulation addresses of data locations in configurable memory 203. Upgraded or substitute data is programmed into the configurable memory 203 at the paired emulation address.Type: ApplicationFiled: March 5, 2008Publication date: February 12, 2009Applicant: ZEROG WIRELESS, INC.Inventor: Paul G. Davis
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Publication number: 20090031093Abstract: A method of operating a memory component that includes a memory core includes receiving, from external control lines, a write command that specifies a write operation. The write command is stored for a first time period after receiving the write command. After the first time period, the write operation is initiated in response to the write command. During the write operation, unmasked portions of received data are written to the memory core, where the unmasked portions of the data are bits of the data that are identified by received mask information as not being masked.Type: ApplicationFiled: September 30, 2008Publication date: January 29, 2009Inventors: Paul G. Davis, Frederick A. Ware, Craig E. Hampel
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Patent number: 7437527Abstract: A method and apparatus for storing data in a memory device is described. The apparatus is configured to perform the following steps. The method employs a two-step technique which allows the out-of-order completion of read and write operations. When a write operation requires a resource needed for the completion of a read operation, the data being written is stored in a write data buffer in the memory device. The write data is stored in the buffer until a datapath is available to communicate the data to the memory device's memory core. Once the resource is free (or the memory device, or its controller force the write to complete) the data is written to the memory core of the memory device using the now-free datapath.Type: GrantFiled: April 9, 2007Date of Patent: October 14, 2008Assignee: Rambus Inc.Inventors: Paul G. Davis, Frederick A. Ware, Craig E. Hampel
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Patent number: 7421548Abstract: A method and apparatus for storing data in a memory device is described. The apparatus is configured to perform the following steps. The method employs a two-step technique which allows the out-of-order completion of read and write operations. When a write operation requires a resource needed for the completion of a read operation, the data being written is stored in a write data buffer in the memory device. The write data is stored in the buffer until a datapath is available to communicate the data to the memory device's memory core. Once the resource is free (or the memory device, or its controller force the write to complete) the data is written to the memory core of the memory device using the now-free datapath.Type: GrantFiled: July 13, 2005Date of Patent: September 2, 2008Assignee: Rambus Inc.Inventors: Paul G. Davis, Frederick A. Ware, Craig E. Hampel
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Publication number: 20080162759Abstract: A method and apparatus for adjusting the performance of a memory system is provided. A memory system comprises a master device and a slave device. A memory channel couples the master device to the slave device such that the slave device receives the system operating information from the master device via the memory channel. The slave device further includes means for tuning circuitry within the slave device such that the performance of the memory system is improved.Type: ApplicationFiled: February 25, 2008Publication date: July 3, 2008Applicant: RAMBUS INC.Inventors: Bruno Werner Garlepp, Pak Shing Chau, Kevin S. Donnelly, Clemenz Portmann, Donald C. Stark, Stefanos Sidiropoulos, Richard M. Barth, Paul G. Davis, Ely K. Tsern
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Patent number: 7360050Abstract: An integrated circuit memory device has a first set of pins to receive, using a clock signal, a row address followed by a column address. The device has a second set of pins to receive, using the clock signal, a sense command and a write command. The sense command specifies that the device activate a row of memory cells identified by the row address. The write command specifies that the memory device receive write data and store the write data at a location, identified by the column address, in the row of memory cells. The write command is posted internally to the memory device after a first delay has transpired from a first time period in which the write command is received at the second set of pins. The write data is received at a third set of pins after a second delay has transpired from the first time period.Type: GrantFiled: March 2, 2007Date of Patent: April 15, 2008Assignee: Rambus Inc.Inventors: Richard M. Barth, Frederick A. Ware, Donald C. Stark, Craig E. Hampel, Paul G. Davis, Abhijit M. Abhyankar, James A. Gasbarro, David Nguyen
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Patent number: 7349279Abstract: A dynamic random access memory device includes banks of dynamic memory cells. The device performs a refresh operation in response to receiving a self refresh command, by refreshing rows of the memory cells located in each of the banks. Further, a refresh frequency for the refresh operation is selected such that the refresh frequency is minimized to conserve power consumed by the memory device while being sufficient to refresh the rows of the memory cells.Type: GrantFiled: November 22, 2006Date of Patent: March 25, 2008Assignee: Rambus Inc.Inventors: Ely K. Tsern, Richard M. Barth, Paul G. Davis, Craig E. Hampel
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Patent number: 7337294Abstract: A method and apparatus for adjusting the performance of a memory system is provided. A memory system comprises a master device and a slave device. A memory channel couples the master device to the slave device such that the slave device receives the system operating information from the master device via the memory channel. The slave device further includes means for tuning circuitry within the slave device such that the performance of the memory system is improved.Type: GrantFiled: December 11, 2006Date of Patent: February 26, 2008Assignee: Rambus Inc.Inventors: Bruno Werner Garlepp, Pak Shing Chau, Kevin S. Donnelly, Clemenz Portmann, Donald C. Stark, Stefanos Sidiropoulos, Richard M. Barth, Paul G. Davis, Ely K. Tsern
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Patent number: 7330953Abstract: A memory system has first, second and third interconnects and an integrated circuit memory device coupled to the interconnects. The second interconnect conveys a write command and a read command. The third interconnect conveys write data and read data. The integrated circuit memory device includes a pin coupled to the first interconnect to receive a clock signal. The memory device also includes a first plurality of pins coupled to the second interconnect to receive the write command and read command, and a second plurality of pins coupled to the third interconnect to receive write data and to assert read data. Control information is applied to initiate the write operation after a first predetermined delay time transpires from when the write command is received. During a clock cycle of the clock signal, two bits of read data are conveyed by each pin of the second plurality of pins.Type: GrantFiled: March 27, 2007Date of Patent: February 12, 2008Assignee: Rambus Inc.Inventors: Richard M. Barth, Frederick A. Ware, Donald C. Stark, Craig E. Hampel, Paul G. Davis, Abhijit M. Abhyankar, James A. Gasbarro, David Nguyen
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Patent number: 7330952Abstract: An integrated circuit memory device includes a first set of pins and a memory core. The first set of pins receive, using a clock signal, a write command and a read command. Control information is issued internally in response to the write command after a predetermined delay time transpires following receipt of the write command, the control information initiating the write operation in the memory device. A second set of pins output the read data after a first delay time transpires from when the read command is received. Each pin of the second set of pins outputs two bits of read data during a clock cycle of the clock signal. The second set of pins also receive write data after a second delay time has transpired from when the write command is received. The second delay time is based on the first delay time.Type: GrantFiled: March 27, 2007Date of Patent: February 12, 2008Assignee: Rambus Inc.Inventors: Richard M. Barth, Frederick A. Ware, Donald C. Stark, Craig E. Hampel, Paul G. Davis, Abhijit M. Abhyankar, James A. Gasbarro, David Nguyen