Patents by Inventor Paul G. Davis
Paul G. Davis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7288973Abstract: A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and voltage shifts after initialization while maintaining the same output data latency. In one embodiment, this circuit is used on a bus-system to re-time data from receive-domain, clocks to transmit-domain clocks. In such a system the phase relationships between these two clocks is set by the device bus location and thus is not precisely known. By supporting arbitrary phase resynchronization, this disclosure allows for theoretically infinite bus-length and thus no limitation on device count, as well as arbitrary placement of devices along the bus. This ultimately allows support of multiple latency-domains for very long buses.Type: GrantFiled: September 27, 2005Date of Patent: October 30, 2007Assignee: Rambus Inc.Inventors: Jared LeVan Zerbe, Michael Tak-kei Ching, Abhijit M. Abhyankar, Richard M. Barth, Andy Peng-Pui Chan, Paul G. Davis, William F. Stonecypher
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Patent number: 7287119Abstract: An integrated circuit memory device having delayed write command processing includes a first set of pins coupled to a memory core, the first set of pins to receive a row address followed by a column address. A second set of pins, coupled to memory core, are used to receive a sense command followed by a write command. The sense command specifies the sensing of a row of memory cells identified by the row address, and the write command specifies that the memory device receive write data and store the write data at a column location identified by the column address. The write command is posted internally to the memory device after a first delay has transpired from when the write command is received at the second set of pins.Type: GrantFiled: March 2, 2007Date of Patent: October 23, 2007Assignee: Rambus Inc.Inventors: Richard M. Barth, Frederick A. Ware, Donald C. Stark, Craig E. Hampel, Paul G. Davis, Abhijit M. Abhyankar, James A. Gasbarro, David Nguyen
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Patent number: 7197611Abstract: A memory device includes an interconnect with mask pins and a memory core for storing data. A memory interface circuit is connected between the interconnect and the memory core. The memory interface circuit selectively processes write mask data from the mask pins or precharge instruction signals from the mask pins.Type: GrantFiled: February 15, 2005Date of Patent: March 27, 2007Assignee: Rambus Inc.Inventors: Richard M. Barth, Frederick A. Ware, Donald C. Stark, Craig E. Hampel, Paul G. Davis, Abhijit M. Abhyankar, James A. Gasbarro, David Nguyen
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Patent number: 7149856Abstract: A method and apparatus for adjusting the performance of a memory system is provided. A memory control device comprises a master device including a frequency detector, a memory channel, and a memory device coupled to the master device via the memory channel. The memory device includes a decoder designed to receive a control signal from the master device. A clock recovery and alignment circuit receives the control signal from the decoder and adjusts the operating frequency of the memory device in response to the control signal.Type: GrantFiled: March 10, 2003Date of Patent: December 12, 2006Assignee: Rambus Inc.Inventors: Bruno Werner Garlepp, Pak Shing Chau, Kevin S. Donnelly, Clemenz Portmann, Donald C. Stark, Stefanos Sidiropoulos, Richard M. Barth, Paul G. Davis, Ely K. Tsern
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Patent number: 7142475Abstract: A dynamic random access memory device includes banks of dynamic memory cells. The device performs a refresh operation in response to receiving a self refresh command, by refreshing rows of the memory cells located in each of the banks. Further, a refresh frequency for the refresh operation is selected such that the refresh frequency is minimized to conserve power consumed by the memory device while being sufficient to refresh the rows of the memory cells.Type: GrantFiled: August 13, 2004Date of Patent: November 28, 2006Assignee: Rambus, Inc.Inventors: Ely K. Tsern, Richard M. Barth, Paul G. Davis, Craig E. Hampel
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Patent number: 7047375Abstract: A method and apparatus for storing data in a memory device is described. The apparatus is configured to perform the following steps. The method employs a two-step technique which allows the out-of-order completion of read and write operations. When a write operation requires a resource needed for the completion of a read operation, the data being written is stored in a write data buffer in the memory device. The write data is stored in the buffer until a datapath is available to communicate the data to the memory device's memory core. Once the resource is free (or the memory device, or its controller force the write to complete) the data is written to the memory core of the memory device using the now-free datapath.Type: GrantFiled: March 24, 2005Date of Patent: May 16, 2006Assignee: Rambus Inc.Inventors: Paul G. Davis, Frederick A. Ware, Craig E. Hampel
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Patent number: 6949958Abstract: A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and voltage shifts after initialization while maintaining the same output data latency. In one embodiment, this circuit is used on a bus-system to re-time data from receive-domain, clocks to transmit-domain clocks. In such a system the phase relationships between these two clocks is set by the device bus location and thus is not precisely known. By supporting arbitrary phase resynchronization, this disclosure allows for theoretically infinite bus-length and thus no limitation on device count, as well as arbitrary placement of devices along the bus. This ultimately allows support of multiple latency-domains for very long buses.Type: GrantFiled: October 28, 2002Date of Patent: September 27, 2005Assignee: Rambus Inc.Inventors: Jared LeVan Zerbe, Michael Tak-kei Ching, Abhijit M. Abhyankar, Richard M. Barth, Andy Peng-Pui Chan, Paul G. Davis, William F. Stonecypher
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Patent number: 6889300Abstract: A method and apparatus for storing data in a memory device is described. The apparatus is configured to perform the following steps. The method employs a two-step technique which allows the out-of-order completion of read and write operations. When a write operation requires a resource needed for the completion of a read operation, the data being written is stored in a write data buffer in the memory device. The write data is stored in the buffer until a datapath is available to communicate the data to the memory device's memory core. Once the resource is free (or the memory device, or its controller force the write to complete) the data is written to the memory core of the memory device using the now-free datapath.Type: GrantFiled: December 11, 2001Date of Patent: May 3, 2005Assignee: Rambus Inc.Inventors: Paul G. Davis, Frederick A. Ware, Craig E. Hampel
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Patent number: 6868474Abstract: A memory device includes an interconnect with mask pins and a memory core for storing data. A memory interface circuit is connected between the interconnect and the memory core. The memory interface circuit selectively processes write mask data from the mask pins or precharge instruction signals from the mask pins.Type: GrantFiled: April 22, 2002Date of Patent: March 15, 2005Assignee: Rambus Inc.Inventors: Richard M. Barth, Frederick A. Ware, Donald C. Stark, Craig E. Hampel, Paul G. Davis, Abhijit M. Abhyankar, James A. Gasbarro, David Nguyen
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Patent number: 6842864Abstract: A method and apparatus for initializing dynamic random access memory (DRAM) devices is provided wherein a channel is levelized by determining the response time of each of a number of DRAM devices coupled to a bus. Determining the response time for a DRAM device comprises writing logic ones to a memory location of the DRAM device using the bus. Subsequently, a read command is issued over the bus, wherein the read command is addressed to the newly-written memory location of the DRAM device. The memory controller then measures the elapsed time between the issuance of the read command and the receipt of the logic ones from the DRAM device, and this elapsed time is the response time of the DRAM device. Following the determination of a response time for each DRAM device, and using the longest response time, a delay is computed for each of the DRAM devices coupled to the bus so that the response time, in clock cycles, of each of the DRAM devices coupled to the bus equals the longest response time.Type: GrantFiled: October 5, 2000Date of Patent: January 11, 2005Assignee: Rambus Inc.Inventors: Richard M. Barth, Ely K. Tsern, Craig E. Hampel, Frederick A. Ware, Todd W. Bystrom, Bradley A. May, Paul G. Davis
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Publication number: 20040168036Abstract: A method and apparatus for adjusting the performance of a memory system is provided. A memory control device comprises a master device including a frequency detector, a memory channel, and a memory device coupled to the master device via the memory channel. The memory device includes a decoder designed to receive a control signal from the master device. A clock recovery and alignment circuit receives the control signal from the decoder and adjusts the operating frequency of the memory device in response to the control signal.Type: ApplicationFiled: March 10, 2003Publication date: August 26, 2004Inventors: Bruno Werner Garlepp, Pak Shing Chau, Kevin S. Donnelly, Clemenz Portmann, Donald C. Stark, Stefanos Sidiropoulos, Richard M. Barth, Paul G. Davis, Ely K. Tsern
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Patent number: 6778458Abstract: A method for reducing the communication overhead over the interface bus to the memory devices for refresh operations. This is done by refreshing multiple banks in response to a single command. Multibank refresh is made possible by varying the current profile for the row sense and row precharge currents during a refresh operation, as compared to normal memory access. Unlike normal memory accesses, data is not needed, and a fast access time is not required. This allows the current to be spread using different circuitry for driving the current to lessen current spikes. The spread current is still maintained within the timing of a normal memory access.Type: GrantFiled: July 22, 2003Date of Patent: August 17, 2004Assignee: Rambus Inc.Inventors: Ely K. Tsern, Richard M. Barth, Paul G. Davis, Craig E. Hampel
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Patent number: 6757789Abstract: The present invention provides various techniques for optimized transfer of information in electronic systems involving memory devices to improve data bandwidth. The invention offers solutions to the problem of packing all of the required information including data, control and address information over a limited number of interconnect lines in an optimized fashion. In one embodiment, the present invention combines different control information, such as row address and bank address information into a unified address field wherein one or more bits can be shared. By sharing bits across various address fields, the present invention conserves bandwidth that is required by the control signals. In another embodiment, the present invention provides various schemes for defining and constructing packets of information that maximize the amount of information carried by a given packet across a limited number of interconnect lines.Type: GrantFiled: January 30, 2002Date of Patent: June 29, 2004Assignee: Rambus, Inc.Inventors: Abhijit M. Abhyankar, Frederick A. Ware, Donald C. Stark, Craig E. Hampel, Paul G. Davis
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Publication number: 20040062120Abstract: A method for reducing the communication overhead over the interface bus to the memory devices for refresh operations. This is done by refreshing multiple banks in response to a single command. Multibank refresh is made possible by varying the current profile for the row sense and row precharge currents during a refresh operation, as compared to normal memory access. Unlike normal memory accesses, data is not needed, and a fast access time is not required. This allows the current to be spread using different circuitry for driving the current to lessen current spikes. The spread current is still maintained within the timing of a normal memory access.Type: ApplicationFiled: July 22, 2003Publication date: April 1, 2004Applicant: Rambus Inc.Inventors: Ely K. Tsern, Richard M. Barth, Paul G. Davis, Craig E. Hampel
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Patent number: 6597616Abstract: A method for reducing the communication overhead over the interface bus to the memory devices for refresh operations. This is done by refreshing multiple banks in response to a single command. Multibank refresh is made possible by varying the current profile for the row sense and row precharge currents during a refresh operation, as compared to normal memory access. Unlike normal memory accesses, data is not needed, and a fast access time is not required. This allows the current to be spread using different circuitry for driving the current to lessen current spikes. The spread current is still maintained within the timing of a normal memory access.Type: GrantFiled: January 29, 2002Date of Patent: July 22, 2003Assignee: Rambus Inc.Inventors: Ely K. Tsern, Richard M. Barth, Paul G. Davis, Craig E. Hampel
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Patent number: 6553452Abstract: A synchronous dynamic random access memory device having an array of dynamic memory cells. The memory device includes input receiver circuitry to sample a value that is representative of a range of temperatures. In addition, the memory device includes a programmable register, coupled to the input receiver circuitry, to store the value that is representative of the range of temperatures.Type: GrantFiled: January 18, 2002Date of Patent: April 22, 2003Assignee: Rambus Inc.Inventors: Bruno Werner Garlepp, Pak Shing Chau, Kevin S. Donnelly, Clemenz Portmann, Donald C. Stark, Stefanos Sidiropoulos, Richard M. Barth, Paul G. Davis, Ely K. Tsern
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Publication number: 20030053489Abstract: A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and voltage shifts after initialization while maintaining the same output data latency. In one embodiment, this circuit is used on a bus-system to re-time data from receive-domain, clocks to transmit-domain clocks. In such a system the phase relationships between these two clocks is set by the device bus location and thus is not precisely known. By supporting arbitrary phase resynchronization, this disclosure allows for theoretically infinite bus-length and thus no limitation on device count, as well as arbitrary placement of devices along the bus. This ultimately allows support of multiple latency-domains for very long buses.Type: ApplicationFiled: October 28, 2002Publication date: March 20, 2003Applicant: Rambus, Inc.Inventors: Jared LeVan Zerbe, Michael Tak-Kei Ching, Abhijit M. Abhyankar, Richard M. Barth, Andy Peng-Pui Chan, Paul G. Davis, William F. Stonecypher
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Patent number: 6513103Abstract: A method and apparatus for adjusting the performance of a memory system is provided. A memory system comprises a master device and a slave device. A memory channel couples the master device to the slave device such that the slave device receives the system operating information from the master device via the memory channel. The slave device further includes means for tuning circuitry within the slave device such that the performance of the memory system is improved.Type: GrantFiled: October 10, 1997Date of Patent: January 28, 2003Assignee: Rambus Inc.Inventors: Bruno Werner Garlepp, Pak Shing Chau, Kevin S. Donnelly, Clemenz Portmann, Donald C. Stark, Stefanos Sidiropoulos, Richard M. Barth, Paul G. Davis, Ely K. Tsern
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Publication number: 20020178324Abstract: A memory device includes an interconnect with mask pins and a memory core for storing data. A memory interface circuit is connected between the interconnect and the memory core. The memory interface circuit selectively processes write mask data from the mask pins or precharge instruction signals from the mask pins.Type: ApplicationFiled: April 22, 2002Publication date: November 28, 2002Applicant: Rambus Inc.Inventors: Richard M. Barth, Frederick A. Ware, Donald C. Stark, Craig E. Hampel, Paul G. Davis, Abhijit M. Abhyankar, James A. Gasbarro, David Nguyen
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Patent number: 6473439Abstract: A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and voltage shifts after initialization while maintaining the same output data latency. In one embodiment, this circuit is used on a bus-system to re-time data from receive-domain, clocks to transmit-domain clocks. In such a system the phase relationships between these two clocks is set by the device bus location and thus is not precisely known. By supporting arbitrary phase resynchronization, this disclosure allows for theoretically infinite bus-length and thus no limitation on device count, as well as arbitrary placement of devices along the bus. This ultimately allows support of multiple latency-domains for very long buses.Type: GrantFiled: October 9, 1998Date of Patent: October 29, 2002Assignee: Rambus IncorporatedInventors: Jared LeVan Zerbe, Michael Tak-kei Ching, Abhijit M. Abhyankar, Richard M. Barth, Andy Peng-Pui Chan, Paul G. Davis, William F. Stonecypher