Patents by Inventor Paul Loewenstein
Paul Loewenstein has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240004795Abstract: A system includes at least one memory controller that partitions at least one memory into a plurality of nodes. Blast zones are formed that each include a predetermined number of nodes. Cache lines are erasure encoded to be stored in one or more blast zones with at least two nodes in a blast zone storing respective portions of a cache line and at least one node in the blast zone storing a parity portion. In one aspect, it is determined that data stored in one or more nodes of a blast zone needs to be reconstructed and stored in one or more spare nodes designated to replace the one or more nodes. Erasure decoding is performed using data from one or more other nodes in the blast zone to reconstruct the data for storage in the one or more spare nodes.Type: ApplicationFiled: June 29, 2022Publication date: January 4, 2024Inventors: Dejan Vucinic, Jaco Hofmann, Paul Loewenstein, Huynh Tu Dang, Marjan Radi
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Patent number: 10999401Abstract: On-die functional blocks may use multiple communication networks to send requests and receive responses. For example, a first functional block may send a request via a first network. In response to receiving the request, a second functional block may respond to the first functional block via a second network. The second functional block may also send any requested data to the first functional block via a third network.Type: GrantFiled: October 22, 2018Date of Patent: May 4, 2021Assignee: Oracle International CorporationInventors: Paul Loewenstein, Robert P. Masleid, Stephen Phillips, Thirumalai Swamy Suresh
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Patent number: 10387314Abstract: A directory structure that may allow concurrent processing of write-back and clean victimization requests is disclosed. The directory structure may include a memory configured to store a plurality of entries, where each entry may include information indicative of a status of a respective entry in a cache memory. Update requests for the entries in the memory may be received and stored. A subset of previously stored update requests may be selected. Each update request of the subset of the previously stored update requests may then be processed concurrently.Type: GrantFiled: August 25, 2015Date of Patent: August 20, 2019Assignee: Oracle International CorporationInventors: Thomas Wicki, Jurgen Schulz, Paul Loewenstein
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Publication number: 20190058779Abstract: A method for communication among multiple on-die functional blocks using multiple communication networks is disclosed. The method may include sending a request from a first functional block via a first network. In response to receiving the request, a second functional block may respond to the first functional block via a second network. The second functional block may also send any requested data to the first functional block via a third network.Type: ApplicationFiled: October 22, 2018Publication date: February 21, 2019Inventors: Paul Loewenstein, Robert P. Masleid, Stephen Phillips, Thirumalai Swamy Suresh
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Patent number: 10110700Abstract: A method for communication among multiple on-die functional blocks using multiple communication networks is disclosed. The method may include sending a request from a first functional block via a first network. In response to receiving the request, a second functional block may respond to the first functional block via a second network. The second functional block may also send any requested data to the first functional block via a third network.Type: GrantFiled: July 21, 2014Date of Patent: October 23, 2018Assignee: Oracle International CorporationInventors: Paul Loewenstein, Robert P. Masleid, Stephen Phillips, Thirumalai Swamy Suresh
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Patent number: 10007629Abstract: A system is disclosed in which the system may include multiple bus switches, and multiple processors. Each processor may be coupled to each bus switch. Each processor may be configured to initiate a transfer of data to a given bus switch, and detect if a respective link to the given bus switch is inoperable. In response to detecting an inoperable link to a first bus switch, a given processor may be further configured to send a notification message to at least one other processor via at least a second bus switch and to remove routing information corresponding to the inoperable link from a first register. The at least one other processor may be configured to remove additional routing information corresponding to the inoperable link from a second register in response to receiving the notification message from the given processor.Type: GrantFiled: January 16, 2015Date of Patent: June 26, 2018Assignee: Oracle International CorporationInventors: Thomas Wicki, David Smentek, Sumti Jairath, Kathirgamar Aingaran, Ali Vahidsafa, Paul Loewenstein
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Patent number: 9898414Abstract: Nodes in a distributed node system are configured to support memory corruption detection when memory is shared between the nodes. Nodes in the distributed node system share data in units of memory referred to herein as “shared cache lines.” A node associates a version value with data in a shared cache line. The version value and data may be stored in a shared cache line in the node's main memory. When the node performs a memory operation, it can use the version value to determine whether memory corruption has occurred. For example, a pointer may be associated with a version value. When the pointer is used to access memory, the version value of the pointer may indicate the expected version value at the memory location. If the version values do not match, then memory corruption has occurred.Type: GrantFiled: October 31, 2014Date of Patent: February 20, 2018Assignee: Oracle International CorporationInventors: Zoran Radovic, Paul Loewenstein, John G. Johnson
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Patent number: 9632883Abstract: An apparatus and method for encoding data are disclosed that may allow for different encoding levels of transmitted data. The apparatus may include an encoder unit and a plurality of transceiver units. The encoder unit may be configured to receive a plurality of data words, where each data word includes N data bits, wherein N is a positive integer greater than one, and encode a first data word of the plurality of data words. The encoded first data word may include M data bits, where M is a positive integer greater than N. Each transceiver unit may transmit a respective data bit of the encoded first data word. The encoder unit may be further configured to receive information indicative of a quality of transmission of the encoded first data word, and encode a second data word of the plurality of data words dependent upon the quality.Type: GrantFiled: December 8, 2014Date of Patent: April 25, 2017Assignee: Oracle International CorporationInventors: Robert P. Masleid, Don Draper, Venkat Krishnaswamy, Paul Loewenstein
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Publication number: 20170060745Abstract: A directory structure that may allow concurrent processing of write-back and clean victimization requests is disclosed. The directory structure may include a memory configured to store a plurality of entries, where each entry may include information indicative of a status of a respective entry in a cache memory. Update requests for the entries in the memory may be received and stored. A subset of previously stored update requests may be selected. Each update request of the subset of the previously stored update requests may then be processed concurrently.Type: ApplicationFiled: August 25, 2015Publication date: March 2, 2017Inventors: Thomas Wicki, Jurgen Schulz, Paul Loewenstein
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Patent number: 9406364Abstract: Embodiments of an apparatus and method for encoding data are disclosed that may allow for reduced simultaneous switching output noise. The apparatus may include a row decode circuit, a column decode circuit, and a memory array. The row decode circuit and column decode circuits may be configured to decode a first portion and a second portion, respectively, of a given data word of a first plurality of data words, where each data word may include N data bits, and where N is an integer greater than one. The memory array may be configured to store a second plurality of data words where each data word may include M data bits, and where M is an integer greater than N. The memory array may be further configured to retrieve a given data word of the second plurality of data words dependent upon the decoded first and second portions.Type: GrantFiled: June 20, 2014Date of Patent: August 2, 2016Assignee: Oracle International CorporationInventors: Robert P. Masleid, Don Draper, Venkat Krishnaswamy, Paul Loewenstein
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Publication number: 20160210255Abstract: A system is disclosed in which the system may include multiple bus switches, and multiple processors. Each processor may be coupled to each bus switch. Each processor may be configured to initiate a transfer of data to a given bus switch, and detect if a respective link to the given bus switch is inoperable. In response to detecting an inoperable link to a first bus switch, a given processor may be further configured to send a notification message to at least one other processor via at least a second bus switch and to remove routing information corresponding to the inoperable link from a first register. The at least one other processor may be configured to remove additional routing information corresponding to the inoperable link from a second register in response to receiving the notification message from the given processor.Type: ApplicationFiled: January 16, 2015Publication date: July 21, 2016Inventors: Thomas Wicki, David Smentek, Sumti Jairath, Kathirgamar Aingaran, Ali Vahidsafa, Paul Loewenstein
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Patent number: 9367472Abstract: Systems and methods for reliably using data storage media. Multiple processors are configured to access a persistent memory. For a given data block corresponding to a write access request from a first processor to the persistent memory, a cache controller prevents any read access of a copy of the given data block in an associated cache. The cache controller prevents any read access while detecting an acknowledgment that the given data block is stored in the persistent memory is not yet received. Until the acknowledgment is received, the cache controller allows write access of the copy of the given data block in the associated cache only for a thread in the first processor that originally sent the write access request. The cache controller invalidates any copy of the given data block in any cache levels below the associated cache.Type: GrantFiled: June 10, 2013Date of Patent: June 14, 2016Assignee: Oracle International CorporationInventors: William H. Bridge, Jr., Paul Loewenstein, Mark A. Luttrell
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Publication number: 20160164539Abstract: An apparatus and method for encoding data are disclosed that may allow for different encoding levels of transmitted data. The apparatus may include an encoder unit and a plurality of transceiver units. The encoder unit may be configured to receive a plurality of data words, where each data word includes N data bits, wherein N is a positive integer greater than one, and encode a first data word of the plurality of data words. The encoded first data word may include M data bits, where M is a positive integer greater than N. Each transceiver unit may transmit a respective data bit of the encoded first data word. The encoder unit may be further configured to receive information indicative of a quality of transmission of the encoded first data word, and encode a second data word of the plurality of data words dependent upon the quality.Type: ApplicationFiled: December 8, 2014Publication date: June 9, 2016Inventors: Robert P. Masleid, Don Draper, Venkat Krishnaswamy, Paul Loewenstein
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Publication number: 20150371693Abstract: Embodiments of an apparatus and method for encoding data are disclosed that may allow for reduced simultaneous switching output noise. The apparatus may include a row decode circuit, a column decode circuit, and a memory array. The row decode circuit and column decode circuits may be configured to decode a first portion and a second portion, respectively, of a given data word of a first plurality of data words, where each data word may include N data bits, and where N is an integer greater than one. The memory array may be configured to store a second plurality of data words where each data word may include M data bits, and where M is an integer greater than N. The memory array may be further configured to retrieve a given data word of the second plurality of data words dependent upon the decoded first and second portions.Type: ApplicationFiled: June 20, 2014Publication date: December 24, 2015Inventors: Robert P. Masleid, Don Draper, Venkat Krishnaswamy, Paul Loewenstein
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Publication number: 20150278103Abstract: Nodes in a distributed node system are configured to support memory corruption detection when memory is shared between the nodes. Nodes in the distributed node system share data in units of memory referred to herein as “shared cache lines.” A node associates a version value with data in a shared cache line. The version value and data may be stored in a shared cache line in the node's main memory. When the node performs a memory operation, it can use the version value to determine whether memory corruption has occurred. For example, a pointer may be associated with a version value. When the pointer is used to access memory, the version value of the pointer may indicate the expected version value at the memory location. If the version values do not match, then memory corruption has occurred.Type: ApplicationFiled: October 31, 2014Publication date: October 1, 2015Inventors: Zoran Radovic, Paul Loewenstein, John G. Johnson
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Publication number: 20150281396Abstract: A method for communication among multiple on-die functional blocks using multiple communication networks is disclosed. The method may include sending a request from a first functional block via a first network. In response to receiving the request, a second functional block may respond to the first functional block via a second network. The second functional block may also send any requested data to the first functional block via a third network.Type: ApplicationFiled: July 21, 2014Publication date: October 1, 2015Inventors: Paul Loewenstein, Robert P. Masleid, Stephen Phillips, Thirumalai Swamy Suresh
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Publication number: 20140365734Abstract: Systems and methods for reliably using data storage media. Multiple processors are configured to access a persistent memory. For a given data block corresponding to a write access request from a first processor to the persistent memory, a cache controller prevents any read access of a copy of the given data block in an associated cache. The cache controller prevents any read access while detecting an acknowledgment that the given data block is stored in the persistent memory is not yet received. Until the acknowledgment is received, the cache controller allows write access of the copy of the given data block in the associated cache only for a thread in the first processor that originally sent the write access request. The cache controller invalidates any copy of the given data block in any cache levels below the associated cache.Type: ApplicationFiled: June 10, 2013Publication date: December 11, 2014Inventors: William H. Bridge, JR., Paul Loewenstein, Mark A. Luttrell
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Publication number: 20070255907Abstract: In one embodiment, a processor comprises a coherence trap unit and a trap logic coupled to the coherence trap unit. The coherence trap unit is also coupled to receive data accessed in response to the processor executing a memory operation. The coherence trap unit is configured to detect that the data matches a designated value indicating that a coherence trap is to be initiated to coherently perform the memory operation. The trap logic is configured to trap to a designated software routine responsive to the coherence trap unit detecting the designated value. In some embodiments, a cache tag in a cache may track whether or not the corresponding cache line has the designated value, and the cache tag may be used to trigger a trap in response to an access to the corresponding cache line.Type: ApplicationFiled: April 28, 2006Publication date: November 1, 2007Applicant: Sun Microsystems, Inc.Inventors: Hakan Zeffer, Erik Hagersten, Anders Landin, Shailender Chaudhry, Paul Loewenstein, Robert Cypher, Zoran Radovic
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Publication number: 20070043933Abstract: We propose a class of mechanisms to support a new style of synchronization that offers simple and efficient solutions to several existing problems for which existing solutions are complicated, expensive, and/or otherwise inadequate. In general, the proposed mechanisms allow a program to read from a first memory location (called the “flagged” location), and to then continue execution, storing values to zero or more other memory locations such that these stores take effect (i.e., become visible in the memory system) only while the flagged memory location does not change. In some embodiments, the mechanisms further allow the program to determine when the first memory location has changed. We call the proposed mechanisms conditional multi-store synchronization mechanisms and define aspects of an instruction set architecture consistent therewith.Type: ApplicationFiled: August 17, 2006Publication date: February 22, 2007Applicant: SUN MICROSYSTEMS, INC.Inventors: Mark Moir, Robert Cypher, Paul Loewenstein
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Publication number: 20070043915Abstract: We propose a class of mechanisms to support a new style of synchronization that offers simple and efficient solutions to several existing problems for which existing solutions are complicated, expensive, and/or otherwise inadequate. In general, the proposed mechanisms allow a program to read from a first memory location (called the “flagged” location), and to then continue execution, storing values to zero or more other memory locations such that these stores take effect (i.e., become visible in the memory system) only while the flagged memory location does not change. In some embodiments, the mechanisms further allow the program to determine when the first memory location has changed. We call the proposed mechanisms conditional multi-store synchronization mechanisms.Type: ApplicationFiled: August 17, 2006Publication date: February 22, 2007Applicant: Sun Microsystems, Inc.Inventors: Mark Moir, Robert Cypher, Paul Loewenstein