Abstract: A method and apparatus are provided which eliminate the need for an active traffic flow control protocol to manage request transaction flow between the nodes of a directory-based, scaleable, shared-memory, multi-processor computer system. This is accomplished by determining the maximum number of requests that any node can receive at any given time, providing an input buffer at each node which can store at least the maximum number of requests that any node can receive at any given time and transferring stored requests from the buffer as the node completes requests in process and is able to process additional incoming requests. As each node may have only a certain finite number of pending requests, this is the maximum number of requests that can be received by a node acting in slave capacity from any another node acting in requester capacity. In addition, each node may also issue requests that must be processed within that node.

Abstract: A multiprocessor computer system has a multiplicity of sub-systems and a main memory coupled to a system controller. Some of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a respective set of master cache tags (Etags), including one Etag for each data block stored by the cache memory. Each data processor includes an interface for sending memory transaction requests to the system controller and for receiving cache transaction requests from the system controller corresponding to memory transaction requests by other ones of the data processors. The system controller includes transaction activation logic for activating each said memory transaction request when it meets predefined activation criteria, and for blocking each said memory transaction request until the predefined activation criteria are met.

Abstract: A multiprocessor computer system is provided having a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-systems in accordance with interconnect control signals received from the system controller. At least two of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a set of master cache tags (Etags), including one cache tag for each data block stored by the cache memory. Each data processor includes a master interface for sending memory transaction requests to the system controller. The system controller processes each memory transaction and maintains a set of duplicate cache tags (Dtags) for each data processor. Finally, the system controller contains transaction execution circuitry for activating a transaction for servicing by the interconnect.

Abstract: A multiprocessor computer system has a multiplicity of sub-systems and a main memory coupled to a system controller. Some of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a respective set of master cache tags (Etags), including one Etag for each data block stored by the cache memory. Each data processor includes an interface for sending memory transaction requests to the system controller and for receiving cache transaction requests from the system controller corresponding to memory transaction requests by other ones of the data processors. The system controller includes transaction activation logic for activating each said memory transaction request when it meets predefined activation criteria, and for blocking each said memory transaction request until the predefined activation criteria are met.

Abstract: A multiprocessor computer system is provided having a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-systems in accordance with interconnect control signals received from the system controller. At least two of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a respective master cache index. Each master cache index has a set of master cache tags (Etags), including one cache tag for each data block stored by the cache memory. Each data processor includes a master interface having master classes for sending memory transaction requests to the system controller. The system controller includes memory transaction request logic for processing each memory transaction request by a data processor. The system controller maintains a duplicate cache index having a set of duplicate cache tags (Dtags) for each data processor.

Abstract: The invention concerns a method of direct measurement of a parameter characterizing a fault on an electricity line 1, such as the distance x or the resistance R.sub.d of the fault, the method being based on Ohm's Law including the line inductance L and the resistances R, R.sub.d. The signals respectively associated with the variation of current i(t) and of voltage v(t) at the measuring point M are operated upon by transfer functions the ratio of which is equal to:(2/.tau.) tan .omega..tau./2,.tau. corresponding to the propagation time of a wave over double the distance between the measuring point M and a zone boundary P. The method thus takes into account the distributed capacitances C of the line.

Abstract: A directional relay for providing indication of the direction of a fault on an electric power transfer network has an adder (9), a subtractor (10) and filters (11) which receive signals from voltage and current transformers (6,7) and derive signals related to fault-induced forward and backward transient waves on the network. To ensure reliable operation even when the relay is close to a low impedance element such as a generator (2), the forward wave related signal is delayed in a delay unit (12) by an amount equal to the propagation time of the wave along the section protected by the relay, before the difference between its square and that of the backward wave related signal are integrated (16) to derive the fault direction signal.

Abstract: A system for identifying which of the phases of an N-phase electric-power transmission network has experienced an electrical disturbance. For each phase there is produced a first signal representative of the transient variations of an electrical parameter of the respective phase, or of a linear combination of at least two of these parameters. A set of N second signals is generated from the product of two linear combinations of at least N-1 signals selected among the first signals. The sum of all coefficients for each linear combination is set to zero, with each of the second signals being related to a given phase. Each of the second signals is then integrated to produce a set of N third signals associated with the respective phases. A fourth signal is generated by combining all of the N first signals in a symmetrical manner with respect to all of the first signals, such that the fourth signal is independent of the associated phases.