Abstract: A packaged integrated circuit (IC) includes a leadframe including a die pad. The packaged IC also includes a first circuit on the die pad, the first circuit having a region. The packaged IC also includes a second circuit on the first circuit, the second circuit being spaced from the region by a gap. The packaged IC also includes an attachment layer between the first and second circuits, the attachment layer and the first and second circuits enclosing at least a part of the gap over the region. The packaged IC also includes a mold compound encapsulating the first and second circuits, the attachment layer, and the at least part of the gap.

Abstract: A packaged integrated circuit (IC) includes a leadframe including a die pad and leads around the die pad, an analog IC die having first bond pads on its active top side, and a second circuit including second circuit bond pads attached to the analog IC die by an attachment layer configured as a ring with a hollow center that provides an inner gap. A bottom side of the analog IC or the second circuit is attached to the die pad. Bond wires couple at least some of the first bond pads or some of the second circuit bond pads to the leads, and there is a second coupling between others of the second circuit bond pads and others of the first bond pads. A mold compound is for encapsulating the second circuit and the analog IC.

Abstract: In some examples, a device comprises a ceramic substrate having a cavity, a die pad in the cavity, and a semiconductor die in the cavity and having a first segment coupled to the die pad and a second segment cantilevered over a floor of the cavity. The device also includes a first conductive member in the cavity, the first conductive member coupled to a second conductive member exposed to an exterior of the ceramic substrate. The device also includes a bond wire coupled to a device side of the semiconductor die and to the first conductive member.

Abstract: An integrated circuit includes a semiconductor substrate and a metallization structure over the semiconductor substrate. The metallization structure includes: a dielectric layer having a surface; a conductive routing structure; and an electronic circuit. Over the surface of the dielectric layer, a material is configured to set or adjust the electronic circuit.

Abstract: An integrated circuit includes a lead frame, a first die, and a second die. The first die is bonded to and electrically connected to the lead frame. The second die is electrically connected to and spaced apart from the first die.

Abstract: A packaged integrated circuit (IC) includes a leadframe including a die pad and leads around the die pad, an analog IC die having first bond pads on its active top side, and a second circuit including second circuit bond pads attached to the analog IC die by an attachment layer configured as a ring with a hollow center that provides an inner gap. A bottom side of the analog IC or the second circuit is attached to the die pad. Bond wires couple at least some of the first bond pads or some of the second circuit bond pads to the leads, and there is a second coupling between others of the second circuit bond pads and others of the first bond pads. A mold compound is for encapsulating the second circuit and the analog IC.

Abstract: A packaged integrated circuit (IC) includes a leadframe including a die pad and leads around the die pad, an analog IC die having first bond pads on its active top side, and a second circuit including second circuit bond pads attached to the analog IC die by an attachment layer configured as a ring with a hollow center that provides an inner gap. A bottom side of the analog IC or the second circuit is attached to the die pad. Bond wires couple at least some of the first bond pads or some of the second circuit bond pads to the leads, and there is a second coupling between others of the second circuit bond pads and others of the first bond pads. A mold compound is for encapsulating the second circuit and the analog IC.

Abstract: A first conductive routing structure is electrically connected to a first electronic component. A second conductive routing structure is electrically connected to a second electronic component. An additive deposition process deposits a material over a surface of a processed wafer to form a conductive or resistive structure, which extends from a portion of the first conductive routing structure to a portion of the second conductive routing structure, to configure a circuit including the first and second electronic components.

Abstract: An integrated circuit includes a semiconductor substrate and a metallization structure over the semiconductor substrate. The metallization structure includes: a dielectric layer having a surface; a conductive routing structure; and an electronic circuit. Over the surface of the dielectric layer, a material is configured to set or adjust the electronic circuit.

Abstract: A first conductive routing structure is electrically connected to a first electronic component. A second conductive routing structure is electrically connected to a second electronic component. An additive deposition process deposits a material over a surface of a processed wafer to form a conductive or resistive structure, which extends from a portion of the first conductive routing structure to a portion of the second conductive routing structure, to configure a circuit including the first and second electronic components.

Abstract: Electronic device manufacturing and configuration methods include performing an additive deposition process that deposits a conductive, resistive, magnetic, semiconductor and/or thermally conductive material over a surface of a processed wafer metallization structure to set or adjust a circuit of a capacitor, an inductor, a resistor, an antenna and/or a thermal component of the metallization structure.

Abstract: Described examples include microelectronic devices and integrated circuits with an active first circuit in a first segment of a first wafer, a second circuit in a second segment of the first wafer, and second and third wafers bonded to different surfaces of the first wafer to provide first and second cavities with surfaces spaced from the first segment. An opening extends through the first wafer between the first and second cavities to separate portions of the first and second segments and to form a sealed cavity that surrounds the first segment. A bridge segment of the first wafer supports the first segment in the sealed cavity and includes one or more conductive structures to electrically connect the first and second circuits.

Abstract: A packaged integrated circuit (IC) includes a leadframe including a die pad and leads around the die pad, an analog IC die having first bond pads on its active top side, and a second circuit including second circuit bond pads attached to the analog IC die by an attachment layer configured as a ring with a hollow center that provides an inner gap. A bottom side of the analog IC or the second circuit is attached to the die pad. Bond wires couple at least some of the first bond pads or some of the second circuit bond pads to the leads, and there is a second coupling between others of the second circuit bond pads and others of the first bond pads. A mold compound is for encapsulating the second circuit and the analog IC.

Abstract: A first conductive routing structure is electrically connected to a first electronic component. A second conductive routing structure is electrically connected to a second electronic component. An additive deposition process deposits a material over a surface of a processed wafer to form a conductive or resistive structure, which extends from a portion of the first conductive routing structure to a portion of the second conductive routing structure, to configure a circuit including the first and second electronic components.

Abstract: Described examples include microelectronic devices and integrated circuits with an active first circuit in a first segment of a first wafer, a second circuit in a second segment of the first wafer, and second and third wafers bonded to different surfaces of the first wafer to provide first and second cavities with surfaces spaced from the first segment. An opening extends through the first wafer between the first and second cavities to separate portions of the first and second segments and to form a sealed cavity that surrounds the first segment. A bridge segment of the first wafer supports the first segment in the sealed cavity and includes one or more conductive structures to electrically connect the first and second circuits.

Abstract: Electronic device manufacturing and configuration methods include performing an additive deposition process that deposits a conductive, resistive, magnetic, semiconductor and/or thermally conductive material over a surface of a processed wafer metallization structure to set or adjust a circuit of a capacitor, an inductor, a resistor, an antenna and/or a thermal component of the metallization structure.

Abstract: A first conductive routing structure is electrically connected to a first electronic component. A second conductive routing structure is electrically connected to a second electronic component. An additive deposition process deposits a material over a surface of a processed wafer to form a conductive or resistive structure, which extends from a portion of the first conductive routing structure to a portion of the second conductive routing structure, to configure a circuit including the first and second electronic components.

Abstract: An integrated circuit includes a lead frame, a first die, and a second die. The first die is bonded to and electrically connected to the lead frame. The second die is electrically connected to and spaced apart from the first die.

Abstract: A capacitive sensor has at least first and second conductive areas so that a first capacitance is formed between the first conductive area and a surface, and a second capacitance is formed between the second conductive area and the surface, and the ratio of the first capacitance to the second capacitance has a predetermined value only when the sensor is at a predetermined distance from the surface.

Abstract: A driver circuit includes a first current source configured to sink part of the current from a power supply through a load and a second current source configured to sink part of the current from the power supply to a return path, bypassing the load, so that the current through the load is the difference between the current from the power supply and the current through the second current source.