Abstract: A method and circuit for selectively timing amplifier stages of a multi-stage reader amplifier for a hard disk drive system. The reader amplifier includes a first stage, second stage and third stage coupled in series. The method includes the steps of powering the first stage, delaying the enabling of the second stage, and delaying the enabling of the third stage, in order to reduce excursions on the third stage output signal. The circuit includes a logic circuit for successively enabling the second and third amplifier stages.

Abstract: A digital temperature monitor (DTM (24) includes a proportional-to-absolute temperature (PTAT) sensor (44) and reference circuit (48) coupled to the inputs of a comparator (42). The DTM (24) monitors the temperature of adjacent and/or proximate integrated circuitry. The method includes the steps of providing a reference signal to the comparator (42), increasing the reference signal voltage, and determining the temperature of an integrated circuit by determining when the reference signal is greater than the PTAT sensor (44) output voltage. The DTM (24) may be implemented as part of a hard-disk drive preamplifier circuit (22).

Abstract: A circuit (30, 40) and method for detecting faults of a write head (18) of a hard-disk drive system (70). A first resistor R1 and a second resistor R2 are coupled to coil L of write head (18). A transistor Q1 is coupled to a common node of resistor R1 and R2. Current I0 is applied to the coil L, and voltages Vab and Vac across the nodes at either end of resistors R1 and R1 are analyzed in order to detect faults on write head coil L. The detection is performed during a quiet mode of the hard-disk drive system (70), so the fault detection is frequency-independent. Open faults are distinguishable from short-to-ground faults by the write fault detection circuit (30, 40).

Abstract: A open circuit detection circuit for a hard disk drive write head, wherein the write head receives write drive signals from a write driver, and wherein the write driver generates a write drive signal in response to write control signals. The circuit includes a pulse width detector, generating a latch control signal in response to the detection of a write control signal having a predetermined duration. The circuit also includes a comparator comparing the write drive signal to a predetermined reference level and generating a comparison output signal indicative of whether the write driver signal is more or less than the predetermined level. A latch is coupled to receive the comparison output signal, the latch being clocked in response to the latch control signals. The latch output provides an indication of an open circuit.