Abstract: The present invention provides the amino acid and nucleotide sequences of a CCV spike gene, and compositions containing one or more fragments of the spike gene and encoded polypeptide for prophylaxis, diagnostic purposes and treatment of CCV infections.

Abstract: The present invention provides polynucleotide molecules encoding portions of the S protein from feline infectious peritonitis virus (FIPV). The present invention further provides polynucleotide molecules encoding the entire S protein or portions thereof from feline enteric coronavirus (FECV). The polynucleotide molecules of the present invention are useful as diagnostic reagents.

Abstract: A signal processing circuit, for each string of a musical instrument which string is individually tuned to a frequency, includes a transducer adjacent to the string and an equalizer connected to an output circuit. To emulate an acoustic instrument, the equalizer is set to emphasize a signal present in a frequency range of the tuned frequency of the string and/or its harmonics. It also de-emphasizes at least low end frequencies below the operating range of the string. A mid-range frequency device is provided in the equalizer to produce characteristic mid-range response for a specific acoustic instrument. If the transducer produces an inherent resonance at a characteristic frequency, the equalizer will also de-emphasize the inherent resonance produced by the transducer at the characteristic frequency of the transducer.

Abstract: The present invention provides an entertainment and passenger service system for use in aircrafts and other passenger vehicles. Video monitors are provided at the passenger seats which are connected to entertainment sources located at an head end location via a direct, individual, point to point signal over a star network. A electronic switching unit is provided to connect the entertainment sources to the video monitors. A communications control unit provides communication connections between the passenger seat and the entertainment sources.

Abstract: The present invention provides the amino acid and nucleotide sequences of a CCV spike gene, and compositions containing one or more fragments of the spike gene for prophylaxis, diagnostic, and treatment of CCV infections.

Abstract: A method and apparatus for efficiently performing a cache operation in a processor (70) for both flushing and non-flushing. One embodiment uses a cache flush control bit (100) in a data cache (90) to determine whether or not to ignore valid bits (130) during a pseudo least recently used (LRU) replacement algorithm. When the replacement algorithm is being used for flushing the data cache (90), the valid bits (130) are not used in order to make the algorithm more efficient. If the valid bits (130) are ignored, then the least recently used bits (120) are used to select the cache line that will be replaced. However, when the replacement algorithm is being used for a non-flushing replacement purpose, the valid bits (130) are used first, followed by the plurality of least recently used bits (120), to select the cache line that will be replaced.

Abstract: A data processor (10) has a cache array (40) and a control unit (58) for storing a number of recently accessed data lines. If an execution unit requests a data line that is not stored in the memory cache (a miss) then the control unit will request the data from an external memory device and allocate a location in the cache array in which it will store the requested data when returned. In the depicted embodiment, the control unit first attempts to allocate an invalid one of N possible locations, where N is the set way associativity of the memory cache. If none of the ways is invalid, then the control unit uses a least recently used (LRU) algorithm to select the location. Therefore, the data cache may be non-blocking up to N times to the same set.

Abstract: A memory cache (46) has a plurality of tag arrays (20, 22, 24, 26), a plurality of comparators (38, 40, 42, 44), a plurality a data arrays (12, 14, 16, 18), and a plurality of sense amplifiers (48, 50, 52, 54). The memory cache executes a parallel tag and data array access but does not enable any sense amplifier until a comparator indicates a cache hit. Consequently, the memory cache is suitable for use where power consumption and speed are equally important design constraints.

Abstract: A memory (10) that has a shorter access time and higher reliability in a special mode of operation. In one form, the memory (10) has a special mode of operation in which multiple memory rows are simultaneously selected. As a consequence, multiple memory cells (44) are used to drive each bit line pair. Using multiple memory cells (44) to drive each bit line pair allows the bit lines to be driven to the proper logic state in a shorter time. This speeds up accesses to memory (10). Using multiple memory cells (44) to drive each bit line pair also improves the reliability of memory (10). Because multiple memory cells (44) are used to drive the same bit line pair, a failure of one memory cell (44) still leaves one or more functioning memory cells (44) to drive the correct logic state on the bit line pair. The memory may be incorporated in a cache controller of a data processing system in which only a part of the memory is being used.

Abstract: A latching sense amplifier (10) has sensing circuitry (12 and 14), latching circuitry (16) and switching circuitry (18). The sense amplifier operates between a first and a second voltage supply level and receives two input voltage levels. In a first mode, the sensing circuitry (12 and 14) generates two AC symmetric outputs representative of the voltage differential between the two input voltages. In a second mode, the latching circuitry (16) receives the two AC symmetric outputs and generates a second pair of outputs. The second pair of outputs is also representative of the voltage differential between the two input voltages. The voltage differential between the second pair of outputs is generally equal to the voltage differential between the first and second voltage supply levels. The switching circuitry (18) configures the sensing circuitry (12 and 14) to operate in conjunction with the latching circuitry (16) to form a cross coupled latch in the second mode.

Abstract: A memory system for translating addresses has an active pull-up transistor per CAM entry for guaranteeing that a valid CAM entry is loaded in a CAM array prior to addressing a RAM entry in A RAM array. The CAM has a load device connected to each entry for dynamically activating each CAM entry during an address translation. The RAM array has a plurality of RAM entries wherein each RAM entry is connected to a predetermined CAM entry by a Match-Line. A predetermined one of a plurality of driver transisors is connected to each active Match-Line for selectively charging each Match-Line to a predetermined active state during an address write operation, thereby reducing power consumed by non-selected CAM entries. Only one Match-line remains active in response to a "Hit" condition. Feedback between each Match-Line to a validity bit cell in each entry of the CAM is used to set each validity bit only after a successful write of a CAM entry.

Abstract: A cache has an address bus for receiving requests for data from a processor and a data bus for providing the requested data to the processor. As part of the mechanism for determining if there is a hit in the cache, the cache has TAG locations for storing TAG addresses. The hit signal is not generated unless a TAG address corresponds to the address received on the address bus. Associated with each TAG location are valid bits, disable bits, and LRU bits. The requested data is contained in data locations in the cache. Each data location has a corresponding TAG location. The disable bits can be set under the control of the processor for the case where a data location is defective. Additionally, in various diagnostic modes, the TAG locations, the valid bits, the LRU bits, and the data locations are directly accessible via the data bus.

Abstract: An electrically programmable memory array having rows and columns of floating gate type memory cells employs alternate output lines and ground lines between the columns of cells, providing a virtual ground arrangement. A row is selected by one part of an address input, and a column selected by another part. An output line on one side of the selected column is activated, and a ground line on the other side. A differential sense amplifier is responsive to the voltage on the selected output line and a reference voltage. The number of transistors needed in the decoder for the row select function is greatly reduced by employing predecoders which perform a 1-of-4 select for each pair of address bits, then using one of these select outputs to activate N multiplexers, and all the others as inputs to a decoder with N outputs to the multiplexers.

Abstract: A memory, which has an amplifying circuit which provides a pair of differential signals representative of data contained in a memory cell selected by an address, has an output driver which receives this pair of differential signals on a pair of input lines. The output driver is tri-stated in response to an address transition so that the output driver provides only either valid data or a high impedance. The data provided by the differential signals is latched on the input lines by data latches after a predetermined time delay if new valid data has not appeared. The data latches used add less capacitance to the pair of input lines than those used previously.

Abstract: A static RAM has a plurality of sub-arrays arranged in rows and columns, each sub-array having word lines running the length of the sub-array in a top to bottom direction, and having bit lines running the width of the sub-array in a left to right direction, and having a word line driver for enabling a selected word line in response to receiving a row select signal corresponding to the selected word line; a global row decoder for providing the row select signals as determined by row address signals; a first plurality of column pre-decoders for performing a partial decode of data provided on the bit lines of a first of the rows of sub-arrays, each column pre-decoder corresponding to a particular sub-array; a second plurality of column pre-decoders for performing a partial decode of data provided on the bit lines of a second of the rows of sub-arrays, each column pre-decoder corresponding to a particular sub-array; and a plurality of sense amplifiers for sensing the output of the first and second column decoders

Abstract: A memory circuit has a plurality of bit line pairs and intersecting word lines with a memory cell located at each such intersection. A column address selects the bit line which is to be accessed and a row address selects the word line which is enabled. In response to being selected, a bit line is coupled to a data line. In response to a column address transition, all of the bit lines are decoupled from the data lines while bit lines are precharged. In response to a row address transition, the word lines are disabled while the bit lines are equilibrated.

Abstract: A memory circuit has a plurality of bit line pairs and intersecting word lines with a memory cell located at each such intersection. A column address selects the bit line which is to be accessed and a row address selects the word line which is enabled. Memory cells along an enabled word line cause the bit lines to develop a voltage differential. In response to a change in the row address the bit lines are equalized and precharged. In response to a change in the column address, the bit lines are precharged without being equalized so that the developed voltage differential on the bit lines is maintained.

Abstract: A memory circuit, in using address transition detection to equilibrate bit lines, generates a summation address transition signal for the row address as well as a summation address transition signal for the column address. There is a transition detector for each address signal. The outputs of the transition detectors for the row address signals are summed in at least two logic stages using CMOS logic gates to generate the summation address signal for the row address. Similarly, the outputs of the transition detectors for the column address signals are summed in at least two logic stages using CMOS logic gates to generate the summation address signal for the column address.

Abstract: A memory circuit is provided which has a select and a deselect mode. The memory circuit, as part of its technique for quickly accessing data, includes circuitry for generating a pulse in response to detecting an address transition. When the memory circuit switches from the deselect mode to the select mode, these appears to be an address transition even when there is not an address transition. In order to prevent a delay associated with interpreting such false transition as an actual transition, the detection of address transitions is suppressed for a predetermined delay time following the transition from the select to deselect modes.

Abstract: An electrically programmable memory array having rows and columns of floating gate type memory cells employs alternate output lines and ground lines between the columns of cells, providing a virtual ground arrangement. A row is selected by one part of an address input, and a column selected by another part. An output line on one side of the selected column is activated, and a ground line on the other side. A differential sense amplifier is responsive to the voltage on the selected output line and a reference voltage. To speed up the access time of the memory, the ground select is implemented and applied first, then the output of the ground select is used to generate the column select. In this manner, the biasing sequence for the array can begin before the decode of the column select has been completed.