Abstract: Transaction code written by the programmer may be translated, replaced or transformed into a code that is configured to implement transactions according to any of various techniques. A compiler may replace programmer written transaction code into code allowing multiple compatible transaction implementation techniques to be used in the same program, and at the same time. A programmer may write transaction code once using familiar coding styles, but the transaction to be effected according to one of a number of compatible alternative implementation techniques. The compiler may enable the implementation of multiple, alternative transactional memory schemes. The particular technique implemented for each transaction may not be decided until runtime. At runtime, any of the various implemented techniques may be used to effect the transaction and if a first technique fails or is inappropriate for a particular transaction, one or more other techniques may be attempted.

Abstract: A sideband scout thread processing technique is provided. The sideband scout thread processing technique utilizes sideband information to identify a subset of processor instructions for execution by a scout thread processor. The sideband information identifies instructions that need to be executed to “warm-up” a cache memory that is shared with a main processor executing the whole set of processor instructions. Thus, the main processor has fewer cache misses and reduced latencies. In one embodiment, a system includes a first processor for executing a sequence of processor instructions, a second processor for executing a subset of the sequence of processor instructions, and a cache shared between the first processor and the second processor. The second processor includes sideband circuitry configured to identify the subset of the sequence of processor instructions to execute according to sideband information associated with the sequence of processor instructions.

Abstract: A processor includes a set of registers, each individually addressable using a corresponding register identification, and plural virtual registers, each individually addressable using a corresponding virtual register identification. The processor transfers values between the set of registers and the plural virtual registers under control of a transfer operation. The processor can include a virtual register cache configured to store multiple sets of virtual register values, such that each of the multiple sets of virtual register values corresponds to a different context. Each of the plural virtual registers can include a valid bit that is reset on a context switch and set when a value is loaded from the virtual register cache. The processor can include a virtual register translation look-aside buffer for tracking the location of each set of virtual register values associated with each context.

Abstract: In a set of registers, each individually addressable by register operations using a corresponding register identification, at least one register of the set of registers is an extended register having multiple storage locations. Values stored in the multiple storage locations are accessed, for example, according to the order in which they have been stored. Less than all of the multiple storage locations are accessible by a register operation at a given time. Older versions of software that do not recognize extended registers identify the extended register as having only one storage location. An extended register can be, for example, a stack register, a queue register, or a mixed register and values stored in the multiple storage locations are read and stored according to the characteristics of the register.

Abstract: Operations including inserted prefetch operations that correspond to addressing chains may be scheduled above memory access operations that are likely-to-miss, thereby exploiting latency of the “martyred” likely-to-miss operations and improving execution performance of resulting code. More generally, certain pre-executable counterparts of likely-to-stall operations that form dependency chains may be scheduled above operations that are themselves likely-to-stall.

Abstract: By maintaining consistency of instruction or operation identification between code prepared for profiling and that prepared using profiling results, efficacy of profile-directed code optimizations can be improved. In particular, profile-directed optimizations based on stall statistics are facilitated in an environment in which correspondence maintained between (i) instructions or operations whose execution performance may be optimized (or which may provide an opportunity for optimization of other instructions or operations) and (ii) particular instructions or operations profiled.

Abstract: The present invention discloses a method and device for ordering memory operation instructions in an optimizing compiler. for a processor that can potentially enter a stall state if a memory queue is full. The method uses a dependency graph coupled with one or more memory queues. The dependency graph is used to show the dependency relationships between instructions in a program being compiled. After creating the dependency graph, the ready nodes are identified. Dependency graph nodes that correspond to memory operations may have the effect of adding an element to the memory queue or removing one or more elements from the memory queue. The ideal situation is to keep the memory queue as full as possible without exceeding the maximum desirable number of elements, by scheduling memory operations to maximize the parallelism of memory operations while avoiding stalls on the target processor.

Abstract: A system and method are provided for efficiently prefetching data in a pointer linked data structure (140). In one embodiment, a data processing system (100) is provided including a processor (110) capable of executing a program, a main-memory (115) and a prefetch engine (175) configured to prefetch data from a plurality of locations in main-memory in response to a prefetch request from the processor. When the data in main-memory (115) has a linked-data-structure having a number nodes (145) each with data (150) stored therein, prefetch engine (175) is configured to traverse the linked-data-structure and prefetch data from the nodes. The prefetch engine (175) is configured to determine from data contained in a prefetched first node (145A) and an offset value a new starting address for a second node (145B) to be prefetched.

Abstract: A sideband scout thread processing technique is provided. The sideband scout thread processing technique utilizes sideband information to identify a subset of processor instructions for execution by a scout thread processor. The sideband information identifies instructions that need to be executed to “warm-up” a cache memory that is shared with a main processor executing the whole set of processor instructions. Thus, the main processor has fewer cache misses and reduced latencies. In one embodiment, a system includes a first processor for executing a sequence of processor instructions, a second processor for executing a subset of the sequence of processor instructions, and a cache shared between the first processor and the second processor. The second processor includes sideband circuitry configured to identify the subset of the sequence of processor instructions to execute according to sideband information associated with the sequence of processor instructions.

Abstract: A sideband VLIW processing technique is provided. The sideband VLIW processing technique utilizes processor executable code and sideband information that identifies grouping and scheduling of the processor instructions to be executed by a sideband VLIW processor. The sideband information is ignored by processors without sideband VLIW processing capability, thus providing backward compatibility for the processor executable code. The sideband VLIW processor does not have the run-time scheduling circuitry of superscalar processors and instead has circuitry to read and interpret sideband information. Multiple sets of sideband information can be provided for a single corresponding executable program, one set for each different sideband VLIW processor implementation.

Abstract: A system that allows a programmer to specify a set of constraints that the programmer has adhered to in writing code so that a compiler is able to assume the set of constraints in disambiguating memory references within the code. The system operates by receiving an identifier for a set of constraints on memory references that the programmer has adhered to in writing the code. The system uses the identifier to select a disambiguation technique from a set of disambiguation techniques. Note that each disambiguation technique is associated with a different set of constraints on memory references. The system uses the selected disambiguation technique to identify memory references within the code that can alias with each other.

Abstract: Additional memory hardware in a computer system which is distinct in function from the main memory system architecture permits the storage and retrieval of prefetch addresses and allows the compiler to more efficiently generate prefetch instructions for execution while traversing pointer-based or recursive data structures. The additional memory hardware makes up a content addressable memory (CAM) or a hash table/array memory that is relatively close in cycle time to the CPU and relatively small when compared to the main memory system. The additional CAM hardware permits the compiler to write data access loops which remember the addresses for each node visited while traversing the linked data structure by providing storage space to hold a prefetch address or a set of prefetch addresses.

Abstract: A method and apparatus for scheduling instructions to provide adequate prefetch latency is disclosed during compilation of a program code in to a program. The prefetch scheduler component of the present invention selects a memory operation within the program code as a “martyr load” and removes the prefetch associated with the martyr load, if any. The prefetch scheduler takes advantage of the latency associated with the martyr load to schedule prefetches for memory operations which follow the martyr load. The prefetches are scheduled “behind” (i.e., prior to) the martyr load to allow the prefetches to complete before the associated memory operations are carried out. The prefetch schedule component continues this process throughout the program code to optimize prefetch scheduling and overall program operation.

Abstract: Counting events during the execution of one or more instructions in a computer system may be accomplished by maintaining a non-speculative counter for counting events occurring in non-speculative instructions, as well as a separate speculative counter for counting events occurring in speculative instructions. Event counters may be used to count individual events occurring during the processing of instructions. When the instruction has been completed, the amount in the event counter corresponding to a particular event for that instruction is added to the amount in the speculative counter corresponding to the event. Then, any retirable instructions are retired. Once an instruction is retired, it is no longer speculative, allowing the amount in the speculative counter to be decremented and the amount in the non-speculative counter to be incremented by the amount in any event counters corresponding to retirable instructions.

Abstract: A processor includes a set of registers, each individually addressable using a corresponding register identification, and plural virtual registers, each individually addressable using a corresponding virtual register identification. The processor transfers values between the set of registers and the plural virtual registers under control of a transfer operation. The processor can include a virtual register cache configured to store multiple sets of virtual register values, such that each of the multiple sets of virtual register values corresponds to a different context. Each of the plural virtual registers can include a valid bit that is reset on a context switch and set when a value is loaded from the virtual register cache. The processor can include a virtual register translation look-aside buffer for tracking the location of each set of virtual register values associated with each context.

Abstract: In a set of registers, each individually addressable by register operations using a corresponding register identification, at least one register of the set of registers is an extended register having multiple storage locations. Values stored in the multiple storage locations are accessed, for example, according to the order in which they have been stored. Less than all of the multiple storage locations are accessible by a register operation at a given time. Older versions of software that do not recognize extended registers identify the extended register as having only one storage location. An extended register can be, for example, a stack register, a queue register, or a mixed register and values stored in the multiple storage locations are read and stored according to the characteristics of the register.

Abstract: A system and method are provided for improved handling of data in a cache memory system (105) for caching data transferred between a processor (110) capable of executing a program and a main-memory (115). The cache memory system (105) has at least one cache (135) with several cache-lines (160) capable of caching data therein. In the method, a cache address space is provided for each cache (135) and special instructions are generated and inserted into the program to directly control caching of data in at least one ofthe cache-lines (160). Special instructions received in the cache memory system (105) are then executed to cache the data. The special instructions can be generated by a compiler during compiling of the program. Where the cache memory system (105) includes a set-associative-cache having a number of sets each with several cache-lines (160), the method can further include the step of determining which cache-line in a set to flush to main-memory (115) before caching new data to the set.

Abstract: Region based optimization may be accomplished by creating dependence graphs for each block and then incrementally computing a single dependence graph for the region. First dependence DAGs are created for each block in the region. This includes defining incoming and outgoing dangling edges for each block. Each dependence DAG is then linked as a control flow graph. Examining of each incoming dangling edge within each block of the region then takes place, with the process traversing each path along the control flow graph in reverse, attempting to match each incoming dangling edge with a corresponding incoming or outgoing dangling edge, stopping only if an outgoing match is found, the same block is examined twice, or the top of the region is found.

Abstract: The present invention discloses a method and device for placing prefetch instruction in a low-level or assembly code instruction stream. It involves the use of a new concept called a martyr memory operation. When inserting prefetch instructions in a code stream, some instructions will still miss the cache because in some circumstances a prefetch cannot be added at all, or cannot be added early enough to allow the needed reference to be in cache before being referenced by an executing instruction. A subset of these instructions are identified using a new method and designated as martyr memory operations. Once identified, other memory operations that would also have been cache misses can “hide” behind the martyr memory operation and complete their prefetches while the processor, of necessity, waits for the martyr memory operation instruction to complete. This will increase the number of cache hits.

Abstract: A system and method are provided for efficient handling of streaming-data in a cache memory system having a cache controller and at least one cache with a number of cache-lines, each cache-line including at least one way capable of caching data. In the method a request to cache data is received in cache controller (140), it is determined from the request whether the data is streaming-data and the data is cached. Optionally, cache-line (160) includes data-store (165) in which the data is cached and tag-field (175) in which information about the data is stored, and the method further includes the step of setting streaming-data-bit (200) in the tag-field to identify the data as streaming-data. In one embodiment, determining whether the data is streaming-data involves recognizing a special instruction to cache streaming-data in a request from a processor (110) executing a program or from a compiler compiling a program.