Abstract: A system and method are provided for efficient handling of streaming-data in a cache memory system (105) having a cache with several cache-lines (160) capable of storing data. In one aspect, a method is provided for determining before storing data to a cache-line if the storing of data will replace earlier data already stored in cache (135). If the storing of data will replace data in the cache (135), it is determined if the data that will be replaced is streaming-data. If the data to be replaced is not streaming-data, it is stored into victim cache (155). However, if the data to be replaced is streaming-data, it is not stored into the victim cache, thereby improving system efficiency by eliminating the copying of data to be replaced and avoiding replacing other earlier data in victim cache (155) that may be needed in the future.

Abstract: Operations including inserted prefetch operations that correspond to addressing chains may be scheduled above memory access operations that are likely-to-miss, thereby exploiting latency of the “martyred” likely-to-miss operations and improving execution performance of resulting code. More generally, certain pre-executable counterparts of likely-to-stall operations that form dependency chains may be scheduled above operations that are themselves likely-to-stall. Techniques have been developed to perform such scheduling. In particular, techniques have been developed that allow scheduled pre-executable operations (including prefetch operations and speculative loads) to be hoisted above intervening speculation boundaries. Speculative copies of dependency chains are employed in some realizations. Aggressive insertion of prefetch operations (including some used as markers) is employed in some realizations. Techniques for scheduling operations (e.g., in a compiler implementation) are described.

Abstract: A heuristic algorithm which identifies loads guaranteed to hit the processor cache which further provides a “minimal” set of prefetches which are scheduled/inserted during compilation of a program is disclosed. The heuristic algorithm of the present invention utilizes the concept of a “cache line” (i.e., the data chunks received during memory operations) in conjunction with the concept of “related” memory operations for determining which prefetches are unnecessary for related memory operations; thus, generating a minimal number of prefetches for related memory operations.

Abstract: By maintaining consistency of instruction or operation identification between code prepared for profiling and that prepared using profiling results, efficacy of profile-directed code optimizations can be improved. In particular, profile-directed optimizations based on stall statistics are facilitated in an environment in which correspondence maintained between (i) instructions or operations whose execution performance may be optimized (or which may provide an opportunity for optimization of other instructions or operations) and (ii) particular instructions or operations profiled.

Abstract: Program code executed in an environment in which latency exists between an execution event and detection of the execution event may be profiled using a technique that includes backtracking from a point in a representation of the program code, which coincides with the detection toward a preceding operation associated with the execution event. Backtracking identifies the preceding operation at a displacement from the detection point unless an ambiguity creating location is disposed between the detection point and the preceding operation. In general, the relevant set of ambiguity creating locations is processor implementation dependent and program code specific; however, branch targets locations, entry points, and trap or interrupt handler locations are common examples. In some realizations, the techniques may be used to associate cache miss (or hit) information with execution of particular memory access instructions.

Abstract: A software method and apparatus for inserting prefetch operations according to data flow analysis. The invention traverses program code to ascertain memory operations and associated address forming operations, and calculates the relative distance between the two operations. If the distance between the two operations is such that a prefetch operation, inserted between the two operations and, in particular to one embodiment, immediately after the address forming operation, would increase the speed of the program when executed, then the prefetch operation is inserted.

Abstract: One embodiment of the present invention provides a system for compiling source code into executable code that performs prefetching for memory operations within critical sections of code that are subject to mutual exclusion. The system operates by compiling a source code module containing programming language instructions into an executable code module containing instructions suitable for execution by a processor. Next, the system identifies a critical section within the executable code module by identifying a region of code between a mutual exclusion lock operation and a mutual exclusion unlock operation. The system schedules explicit prefetch instructions into the critical section in advance of associated memory operations. In one embodiment, the system identifies the critical section of code by using a first macro to perform the mutual exclusion lock operation, wherein the first macro additionally activates prefetching.

Abstract: One embodiment of the present invention provides a system for compiling source code into executable code that performs prefetching for memory operations within regions of code that tend to generate cache misses. The system operates by compiling a source code module containing programming language instructions into an executable code module containing instructions suitable for execution by a processor. Next, the system runs the executable code module in a training mode on a representative workload and keeps statistics on cache miss rates for functions within the executable code module. These statistics are used to identify a set of “hot” functions that generate a large number of cache misses. Next, explicit prefetch instructions are scheduled in advance of memory operations within the set of hot functions.

Abstract: Apparatus, methods, and computer program products are disclosed that improve the operation of a computer that uses a top-of-stack cache by reducing the number of overflow and underflow traps generated during the execution of a program. The invention maintains a predictor value that controls the number of stack elements that are spilled from, or filled to, the top-of-stack cache in response to an overflow trap or an underflow trap (respectively). The predictor reflects the history of overflow traps and underflow traps.

Abstract: Apparatus, methods, and computer program products are disclosed that improve the operation of a computer that uses a top-of-stack cache by reducing the number of overflow and underflow traps generated during the execution of a program. An exception history is maintained that tracks recent occurrences of overflow and underflow exception traps. This exception history is hashed with the address of the computer instruction that caused the exception to generate an index into a set of predictors. Thus, a predictor is used that is responsive to the current exception history of the top-of-stack cache.

Abstract: A system and process for efficiently determining absolute addresses for an intermediate code model of an address space are described. A processor interfaces to a main memory comprising a plurality of addressable locations. Each such addressable location is referenced by an absolute address having a maximum size directly proportional to the total number of the addressable locations in the main memory. The absolute addresses form the address space. Source code is supplied specifying program routines which each include at least one reference to an absolute address within the address space. A translator interfaces with the main memory and the storage device. Object code is generated from the source code program routines. Each such absolute address reference in the source code program routines is instantiated with a code sequence for referencing a subset of the address space.