Abstract: A portable computer and corresponding docking station, where the portable computer may be inserted into or removed from the docking station without concern relating to the state of either the portable computer or of the docking station. The hot docking sequence is performed by establishing a direct connection to the primary PCI bus without the risk of any possible system damage, file damage, or data loss. This can be accomplished even while the portable computer system is powered on and is actively running. The present invention prevents glitches from occurring in pre-existing pins and adds four new pins to implement this novel hot docking sequence. Furthermore, hot undocking can be readily performed as well by basically reversing the docking sequence.

Abstract: The present invention comprises a multiple functional block integrated circuit device for connecting to an external peripheral component interconnect (PCI) bus. The present invention includes an integrated circuit adapted to be coupled to an external PCI bus. The integrated circuit includes a plurality of functional blocks. Each of the plurality of functional blocks performs a function and comprises either a master functional block or a target functional block. A target bus adapted to transmit data signals is integral with the integrated circuit. The target bus is coupled to each of the plurality of functional blocks. A master bus adapted to transmit data signals is also integral with the integrated circuit. The master bus is coupled to each master functional block. A target bus interface integral with the integrated circuit is coupled to the target bus.

Abstract: The present invention relates to a system and method for implementing peripheral device bus mastering via a general purpose list processor. The system is comprised of four main elements: a bus controller, a DMA controller, a list processor, and a device controller. The system operates under two modes of operation. The two modes arise from the two distinct modules: the DMA controller and the list processor. The first mode of operation is a single buffer transfer mode which is directly compatible with a distributed DMA model. Under this mode, distributed DMA registers within the DMA controller are programmed to transfer a single contiguous buffer of data. The second mode of operation is a multiple buffer transfer mode which uses linked lists of buffer transfer descriptors to program the distributed DMA registers within the DMA controller and initiates transfers independent of software.

Abstract: The present invention comprises a smart retry system for a PCI (peripheral component interconnect) agent in a PCI bus system. The system of the present invention includes an initiator PCI agent and a retry delay register coupled to the initiator PCI agent. The initiator PCI agent is adapted to couple to a PCI bus to communicate with a target PCI agent, via the PCI bus, by initiating a data transaction. The retry delay register is coupled to the PCI agent and the PCI bus. The retry delay register is adapted to receive a delay input via the PCI bus. The delay input describes a latency period of the target PCI agent, wherein the latency period is the amount of the delay. The retry delay register couples the delay input to the initiator PCI agent such that the initiator PCI agent initiates a retry at the expiration of the latency period of the target PCI agent in order to efficiently execute an access to the target PCI agent.

Abstract: A multiple peripheral component interconnect (PCI) agent integrated circuit device for connecting to an external PCI bus. In one embodiment, the present multiple PCI agent integrated circuit device includes, an integrated circuit which is adapted to be coupled to an external PCI bus. The integrated circuit includes an internal PCI bus built in. The internal PCI bus is adapted to transmit data signals thereon, and is further adapted to couple to the external PCI bus via a connector. A plurality of PCI agents are built into the integrated circuit, wherein each of the plurality of PCI agents are capable of performing an independent function. Each of the plurality of PCI agents are coupled to the internal PCI bus. A predictive arbiter is built into the integrated circuit and is coupled to both the internal PCI bus and to the plurality of PCI agents. The predictive arbiter arbitrates between the PCI agents for ownership of the internal PCI bus.

Abstract: The present invention is a desktop personal computer (PC) system having peripheral device bus mastering. The system has a Direct Memory Access (DMA) controller for transferring data to and from the memory of the desktop PC system. A hardware state machine is used for programming the DMA controller, generating and sending command signals, and receiving completion status after the transfer of data is complete. A bus controller is used for implementing a memory data transfer request from the DMA controller means and said hardware state machine means. A device controller, either a Universal Serial Bus (USB) controller or an Infrared Data Association (IrDA) controller, is used for receiving and responding to the command signals from the hardware state machine means, transferring data to and from the DMA controller means, and generating and returning a completion status to the hardware state machine means after the transfer of data is complete.

Abstract: A system and method for preventing contention in a shared memory environment. In one embodiment, a first processor reads a traffic controller which is coupled to a shared memory and to a second processor. The first processor writes its identifier into the traffic controller provided that the traffic controller does not already have an identifier corresponding to the second processor stored therein. If the traffic controller does have an identifier corresponding to the second processor stored therein, the first processor periodically reads the traffic controller until the traffic controller does not have an identifier corresponding to the second processor stored therein. Once the traffic controller has the identifier corresponding to the first processor stored therein, the traffic controller allows the first processor to control access to the shared memory.

Abstract: A system and method for determining which of plurality of peripheral components will have access to a peripheral component interconnect (PCI) bus when none of the plurality of peripheral components is currently requesting access to the PCI bus. In one embodiment a history buffer records all requests by a plurality of peripheral components for access to the PCI bus. The present invention then determines which of the plurality of peripheral components requests access to the PCI bus most often. Next, the present invention grants the peripheral component which requests access to the PCI bus most often access to the PCI bus when no other peripheral component is requesting access to the PCI bus. In so doing, the present invention "parks" the PCI bus on the peripheral component which has, in the past, requested access to the PCI bus most often.

Abstract: A reprogrammable state machine which allows the state flow and control outputs to be reprogrammed without requiring modification of the state machine. The reprogrammable state machine uses a reprogrammable logic unit to generate the state transitions and output transitions for each state of the reprogrammable state machine. A memory control unit is used to program the state machine reprogrammable logic unit with default settings for the state transitions and output transitions for each state of the reprogrammable state machine. The memory control unit is also used to reprogram the state machine reprogrammable logic unit with modified settings for the state transitions and output transitions for each state of the reprogrammable state machine which needs to be modified.

Abstract: The present invention relates to a clock recovery system which allows for stable clock information to be extracted from a serial data stream with defined jitter characteristics. The clock recover circuit is comprised of a flip flop which is used for receiving the serial data stream and for outputting stable clock information. A sampling clock circuit is coupled to the flip flop for sending a signal which reflects a center area of each bit period in the serial data stream when a transition occurs in the serial data stream.

Abstract: The present invention is a desktop personal computer (PC) system having peripheral device bus mastering. The system has four main elements: a Direct Memory Access (DMA) controller, a hardware state machine, a bus controller, and a device controller. The device controller may be an IDE hard disk controller which is able to generate long streams of data in an intermittent fashion wherein any single stream of data is targeted to a number of different host memory locations. The device controller may also be an ECP parallel port controller which interfaces with a number of different peripheral devices over a parallel bus wherein each peripheral device appears to the system as a separate and independent data path.

Abstract: A patch mechanism for dynamic modification of the behavior of a state machine without interfering with normal operation of the state machine when modification is not required. The patch mechanism uses a programmable logic array for storing a modified transition and a modified output transition for an individual state of the state machine which is to be modified. A pair of multiplexer having inputs coupled to the state machine and inputs coupled to the programmable logic array are used for allowing the state machine to select either the current transition and the current output transition both defined by the state machine, or a modified transition and a modified output transition if a modification of the present state is required. A logic circuit coupled to the state machine and to both multiplexers will signal both multiplexers when it is valid to modify the present state to the modified transition and the modified output transition.

Abstract: The present invention relates to a system and method for implementing peripheral device bus mastering in a mobile computer system. The system uses the mobile computer system's microcontroller for programming a DMA controller, generating and sending command signals, and receiving completion status after transfer of data is complete. The micro-controller accesses a data buffer descriptor list. The data buffer descriptor list describes each data transfer that the micro-controller initiates, controls, and completes. The Direct Memory Access controller which is programmed by the micro-controller transfers data to and from a memory section of the mobile computer system. A bus controller is used for implementing a memory data transfer request from the DMA controller means and the micro-controller means.

Abstract: The present invention is a system and method for implementing peripheral device bus mastering in a mobile computer system. The system uses the micro-controller of the mobile computer system to program a DMA controller. The DMA controller transfers data to and from the memory of the mobile computer system. A bus controller which is coupled to both the micro-controller and the DMA controller implements a memory data transfer request from the DMA controller and the micro-controller. A device controller, either a IDE hard disk controller or an ECP parallel port controller, is also coupled to the DMA controller and the micro-controller. The device controller receives and responds to the command signals from the micro-controller by transferring data to and from the DMA controller means and generating a completion signal when the transfer is complete.

Abstract: The present invention relates to a system that can combine data packets from two serial data streams to provide a single uncorrupted serial data output. The system is comprised of an internal data source and an external data source which each generates serial bit packets containing system information. The outputs of both the internal and external sources are coupled to a packet arbiter which combines the serial bit packet from the internal data source with the serial bit packet from the external data source to form an uncorrupted combined serial data output stream.