Abstract: A connection between a source node and a destination node is automatically routed and switched in a WDM photonic network, on receipt of a connection request. A switching and routing mechanism selects a plurality of valid link paths using a path tree, where invalid branches are eliminated based on constraints received in the connection request, and on a link and path cost functions. A regenerator placement tree is used for determining a plurality of viable regenerator paths for each valid link path. On the regenerator placement tree, non-viable branches are eliminated based on constraints received with the request and on regenerator availability at the intermediate nodes along the respective path, and on the specification of these available regenerators. Next, the switching and routing mechanism assigns a set of wavelengths to each viable regenerator path, and estimates the performance of the path using a Q estimator.

Abstract: The present invention provides a data processing apparatus and method for controlling access to a memory in the data processing apparatus. The apparatus comprises a processor operable in a plurality of modes and a plurality of domains, said plurality of domains comprising a secure domain and a non-secure domain, said plurality of modes including at least one non-secure mode being a mode in the non-secure domain and at least one secure mode being a mode in the secure domain. The processor is operable such that when executing a program in a secure mode the program has access to secure data which is not accessible when the processor is operating in a non-secure mode. A memory is operable to store data required by the processor and comprises secure memory for storing secure data and non-secure memory for storing non-secure data, the processor being operable to issue a memory access request when access to an item of data in the memory is required.

Abstract: A programmable waveform ballast has a power supply and a waveform generator. The power supply provides, from a power source, a variable power to a discharge lamp. The waveform generator is coupled to the power supply and is programmable to produce a plurality of waveforms. The waveform generator controls the power supply to apply the variable power to the discharge lamp in accordance with a programmed waveform.

Abstract: An optical disc of one embodiment of the invention is disclosed that includes a first surface, a second surface, an optically writable label area, and an optically writable data area. The first and the second surfaces are oppositely situated to one another. The label area is on one of the first and the second surfaces. The data area is on one of the first and the second surfaces. The mechanism aids proper focusing of an optical beam of an optical disc device on the optically writable label area and on the optically writable data area.

Abstract: An image projection system is provided that includes a portable projector, where the projector includes a light engine, and a projector housing having a closed configuration and an open configuration, where in the closed configuration the projector housing at least partially encloses the light engine, and in the open configuration the projector housing supports the light engine.

Abstract: An image projection system is provided that includes a portable projector, where the projector includes a light engine, and a projector housing having a closed configuration and an open configuration, where in the closed configuration the projector housing at least partially encloses the light engine, and in the open configuration the projector housing supports the light engine.

Abstract: A digital micromirror device arrangement and devices using the arrangement are disclosed. The arrangement includes a digital micromirror device (DMD) having an active area, a cover plate disposed substantially adjacent to the DMD and having a thickness and a light blocking area having an aperture formed therein. The active area is adapted to receive incoming light and to reflect the incoming light as outgoing light. The light-blocking layer is offset from a plane of the active area by at least the thickness of the cover plate and is adapted to block light from passing therethrough. The aperture is dimensioned to produce a beam of outgoing light having desired dimensions.

Abstract: A technique is described to reduce overfill of light that has exited a light integrating device and is applied to an optical modulator in the form of an illuminating pattern. The illumination reduction technique makes the illuminating pattern more closely conform to a active planar surface of the optical modulator by at least partially providing anamorphic magnification of the illuminating pattern.

Abstract: A method of producing a light beam for a display system includes generating a light beam having a transverse cross section that is elongate along a longitudinal axis, and moving a plurality of beam-modifying optical elements sequentially along a travel path that intersects the light beam with the light beam cross-section longitudinal axis oriented transverse to the travel path.

Abstract: A method of producing a light beam for a display system includes generating a light beam having a transverse cross section that is elongate along a longitudinal axis, and moving a plurality of beam-modifying optical elements sequentially along a travel path that intersects the light beam with the light beam cross-section longitudinal axis oriented transverse to the travel path.

Abstract: The present invention relates to a technique for accessing memory units in a data processing apparatus. The data processing apparatus comprises of plurality of memory units for storing data values, a processor core for issuing an access request specifying an access to be made to the memory units in relation to a data value, and a memory controller for performing the access specified by the access request. Attribute generation logic is provided for determining from the access request one or more predetermined attributes verifying which of the memory units should be used when performing the access. However, the memory controller does not wait until such determination has been performed by the attribute generation logic before beginning the access.

Abstract: A method for color management in a display system based on perception. A plurality of images may be displayed to a viewer using an additive display device. Each image of the plurality may have a different color adjustment and at least two colors. An input may be received from the viewer selecting an image of the plurality based on the viewer's color perception of such image relative to other images of the plurality. Subsequent images may be displayed according to the different color adjustment of the image selected.

Abstract: An optical disc of one embodiment of the invention is disclosed that includes a first surface, a second surface, an optically writable label area, and an optically writable data area. The first and the second surfaces are oppositely situated to one another. The label area is on one of the first and the second surfaces. The data area is on one of the first and the second surfaces. The mechanism aids proper focusing of an optical beam of an optical disc device on the optically writable label area and on the optically writable data area.

Abstract: The present invention provides a data processing apparatus and method for managing access to a memory within the data processing apparatus. The data processing apparatus comprises a processor operable in a plurality of modes and a plurality of domains, said plurality of domains comprising a secure domain and a non-secure domain, said plurality of modes including at least one non-secure mode being a mode in the non-secure domain and at least one secure mode being a mode in the secure domain, said processor being operable such that when executing a program in a secure mode said program has access to secure data which is not accessible when said processor is operating in a non-secure mode. Further, a memory is provided for storing data required by the processor, and consists of secure memory for storing secure data and non-secure memory for storing non-secure data.

Abstract: The present invention provides a data processing apparatus and method for controlling access to a memory. The data processing apparatus has a secure domain and a non-secure domain, in the secure domain the data processing apparatus having access to secure data which is not accessible in the non-secure domain. The data processing apparatus comprises a device coupled to a memory via a device bus, and operable, when an item of data in the memory is required by the device, to issue onto the device bus a memory access request pertaining to either the secure domain or the non-secure domain. The memory is operable to store data required by the device, and contains secure memory for storing secure data and non-secure memory for storing non-secure data.

Abstract: The present invention provides a data processing apparatus and method for controlling access to a memory in the data processing apparatus. The apparatus comprises a processor operable in a plurality of modes and a plurality of domains, said plurality of domains comprising a secure domain and a non-secure domain, said plurality of modes including at least one non-secure mode being a mode in the non-secure domain and at least one secure mode being a mode in the secure domain. The processor is operable such that when executing a program in a secure mode the program has access to secure data which is not accessible when the processor is operating in a non-secure mode. A memory is operable to store data required by the processor and comprises secure memory for storing secure data and non-secure memory for storing non-secure data, the processor being operable to issue a memory access request when access to an item of data in the memory is required.

Abstract: A valid memory 2 is provided storing valid words 8 with bit positions indicating whether corresponding cache lines within a cache memory 7 store valid data. Flip-flop circuits 4 are provided to indicate whether or not the valid words 8 within the valid memory 2 are themselves valid. The number of valid words 8 corresponding to an individual flip-flop circuit 4 varies in dependence upon the size of the valid memory 2. Thus, for example, a single flip-flop circuit 4 may indicate whether one, two, four or eight valid words 8 from the valid memory 2 are storing valid data depending upon the particular size of the valid memory 2 employed.

Abstract: A display system is configured to produce a color image formed of a plurality of differently colored images and may include at least one light source that directs light along an optical path, and at least one filter having a given optical filter characteristic. The display system may be selectively operable in a first state in which the optical path does not pass through a first filter during production of the plurality of differently colored images to form a color image having a first optical characteristic, and in a second state in which the optical path passes through the first filter during production of the plurality of differently colored images to form a color image having a second optical characteristic different than the first optical characteristic.

Abstract: An apparatus (10) for modulating fluid flow which comprises a first flow path (13) and a second flow path. The second flow path is transverse to the first flow path (13), and has a fluid inlet (31) which opens onto the first flow path (13). The fluid inlet (31) is such that a portion of fluid flowing along the first flow path (13) is diverted into the second flow path. The position of the fluid inlet (31) is set in relation to the direction of fluid flow in the first flow path (13) and in relation to the extent of fluid to be diverted from the first flow path (13) into the second flow path.

Abstract: The present invention relates to the management of caches in a data processing apparatus. An ‘n’-way set-associative cache is disclosed, each way comprises a plurality of cache lines, each of said plurality of cache lines comprising a plurality of data words, each of said plurality of data words having associated therewith a unique address. The unique address includes an address portion. The ‘n’-way set-associative cache comprises a cache memory comprising ‘n’ memory units, each of the ‘n’ memory units having a plurality of entries, respective entries in each of the ‘n’ memory units being associated with the same address portion and being operable to store a data word having that same address portion within its unique address.