Abstract: Test apparatus for testing an integrated circuit The invention relates to a test apparatus for testing an integrated circuit, particularly a DDR semiconductor memory, having at least one data connection for inputting at least one data signal, at least one DQS control connection for inputting at least one unaltered-frequency DQS signal, a device for phase shifting which is designed to take the unaltered-frequency DQS signal and produce a phase-shifted DQS signal, and a combinational logic device which is connected downstream of the device and which logically combines the unaltered-frequency DQS signal with the phase-shifted DQS signal to produce an altered-frequency DQS signal which has a frequency that is increased compared with the frequency of the unaltered-frequency DQS signal and which is provided for latching the data signals or as a clock signal. The invention also relates to a method for operating a test apparatus of this type.

Abstract: The invention provides a method for setting and controlling a read latency (L) by means of a FIFO-based read latency control circuit for a read access to a semiconductor memory, having the method steps of providing a common internal clock signal; generating an internal first clock signal and an internal second clock signal, which is different from the first clock signal, from the common clock signal; generating an output pointer for reading out the read data from the first clock signal; generating an input pointer for reading in the read data from the second clock signal; initializing the input and output pointers by allocating a defined, fixedly predetermined time offset between output pointer and input pointer. The invention furthermore provides a corresponding circuit arrangement for carrying out the method.

Abstract: The invention relates to a method for controlling write access to a semiconductor memory, particularly a DDR graphics memory, in which a multiplicity of data packets are written to the semiconductor memory per data burst, in which write access is initiated by a write command and the data packets which are to be written to the memory are latched under the control of a cycle of a data strobe write clock control signal, where the data packets are latched by alternately using a respective falling and rising edge of the data strobe write clock control signal, and where the data strobe write clock control signal has a defined state at the start of the write operation. The invention also relates to a circuit arrangement for carrying out the method.

Abstract: Integrated circuit with a parallel-serial converter The invention relates to an integrated circuit and method for time-offset provision of input data for a parallel-serial converter, in particular for or in a DDR semiconductor memory, having at least n input terminals at which at least n data packets are present in parallel, a delay device arranged in a manner connected downstream of the input terminals, at least some of the data packets present on the input side being output in time-offset fashion with respect to one another by said delay device, a parallel-serial converter arranged in a manner connected downstream of the delay device, which parallel-serial converter performs a conversion of the data packets that are present in parallel and are time-offset with respect to one another into an output data signal comprising the time-offset data packets in serial form, and an output terminal for outputting the output data signal.

Abstract: The invention relates to a parallel-serial converter for converting parallel data into serial data, in particular for or in a DDR semiconductor memory, having at least n input terminals at which n data signals are present in parallel, an output terminal for outputting a serial data signal, a controllable latch connected to the input terminals on the input side, a common storage node, which is connected to outputs of the latch and which holds a data signal of the controllable latch present last, a controllable bypass device, which has an input, which is coupled to the storage node on the output side and which has a control terminal, via which a predeterminable state present at the input of the bypass device can be switched onto the storage node. The invention furthermore relates to a semiconductor memory having such a parallel-serial converter and to a method for operating such a parallel-serial converter.

Abstract: Register for the parallel-serial conversion of data having a plurality of cyclically driven shift registers (2), each comprising series-connected data holding elements (3), each data holding element (3) being connected to a data input line (5), each shift register (2), upon receiving an input control signal (INP) for the shift register (2), loading the data present on the data input lines (5) into the data holding elements (3) connected thereto; each shift register (2), upon receiving an output control signal (OUTP) for the shift register (2), outputting the datum buffer-stored in the last data holding element of the shift register (2), in which case there is connected downstream of each shift register (2) a further data holding element (10), which, upon receiving an input control signal (INP) for loading the preceding shift register (2), is preloaded with the datum for the first data holding element (3-3) of the shift register (2) and, upon reception of the output control signal (OUTP) for the shift register

Abstract: An integrated memory has row lines, column lines and column selection lines for activating read/write amplifiers. In each case, one group of a predetermined number of memory cells belongs to a row and a column address. Furthermore, the memory has a number of connecting pads corresponding to the predetermined number. Each memory cell in a group of memory cells is associated with one of the connecting pads. A control circuit for controlling the memory access is designed and can be operated such that, with a column address, it activates at least two different column selection lines. One of the column selection lines is activated for two or more column addresses. The delay times and the line lengths on the memory chip can thus be reduced in size.

Abstract: An integrated circuit includes a processing circuit with at least one first and second input connected to a connection for obtaining a control clock. The first and second input are for receiving at least one first and second clock signal that each are derived from the control clock and that are shifted in phase with respect to one another. A third clock signal is generated from the first and second clock signals, and is at a higher frequency than the frequency of the control clock for controlling operation of the circuit. The third clock signal is output at an output. Since the frequency of the third clock signal is greater than the frequency of the control clock, the circuit can, however, be operated over its full frequency range, by using a test unit to supply a control clock at a lower frequency.

Abstract: Latency time circuit for an S-DRAM, which is clocked by a high-frequency clock signal for producing a delayed data enable control signal for synchronous data transfer through a data path of the S-DRAM, having at least one controllable latency time generator for delaying a decoded data enable control signal with an adjustable latency time, characterized by at least one comparison circuit, which compares the cycle time of the high-frequency clock signal with a predetermined decoding time and by a signal delay circuit which can be switched on by means of the comparison circuit in order to delay the decoded data enable control signal with a predetermined delay time, in which the signal delay circuit is switched on by the comparison circuit when the cycle time of the clock signal is in a limit time region which is located about the predetermined decoding time.

Abstract: Latency time circuit for an S-DRAM (1), which is clocked by a high-frequency clock signal (CLK), for producing a delayed data enable signal for synchronous data transfer through a data path (38) of the S-DRAM (1), having a controllable latency time generator (57) for delaying a decoded external data enable signal (PAR) with an adjustable latency time, which a comparison circuit (60) which compares a cycle time (tcycle) of the high-frequency clock signal (CLK) with a predetermined signal delay time of the data path (38), and reduces the latency time of the latency time generator (57) by the cycle time if the signal delay time of the data path (38) is greater than the cycle time (tcycle) of the clock signal (CLK)

Abstract: The invention relates to a DDR memory and to a storage method for storing data in a DDR memory having a plurality of memory cells which each have a prescribed word length, in which a serial data input is used to read in serial data on a rising or falling edge of the data clock signal, and a serial-parallel converter is used to put together a prescribed number of data items from the data read in to give a prescribed number of words from data words having the prescribed word length. To make transferring the data from one synchronization area to another synchronization area, and resynchronization thereof, more reliable, the invention involves an interface memory copying the at least one data word from the serial-parallel converter upon receipt of a copy signal which is synchronous with the data block signal and outputting it to a bus upon receipt of an output signal which is synchronous with the system clock signal.

Abstract: Control circuit for a data path of an S-DRAM which is clocked by a high-frequency clock signal, having a programmable mode register for storing a latency value; a latency generator for temporally delaying a data path control signal, generated by an internal sequence controller, with a switchable latency; a latency decoder, which switches the latency generator in a manner dependent on the latency value stored in the mode register, provision being made of at least one signal delay element, which can be switched in by the latency decoder and serves for the signal delay of the data path control signal with a specific delay time, the latency decoder switching in the associated signal delay element if the stored latency value is high.

Abstract: In a method for reducing interferences in a voice signal, a noise reduction method is applied to the voice signal, and spectral psychoacoustic masking is taken into account. A spectral masking curve is determined both for the input signal and the output signal of the noise reduction method. By comparing the signal portions exceeding the respective masking curve, newly-audible portions are detected in the form of interference in the output signal and subsequently damped selectively.

Abstract: Integrated circuits, in particular memory chips of the DDR SDRAM type, are tested in a parallel manner. In order to prevent the circuits from being driven relative to one another during a test operation, an input terminal that is already connected to a channel of an automatic test machine anyway is connected to a switching device, by which the output drivers can be turned off in a manner dependent on the control signal that can be fed in at the input terminal. The switching device preferably contains a demultiplexer and also a multiplexer. The demultiplexer can be driven by a test control signal that is additionally generated besides the test control signal. The input terminal is connected to a tester channel anyway during test operation, with the result that no additional external outlay arises.

Abstract: Register for the parallel-serial conversion of data having a plurality of cyclically driven shift registers (2), each comprising series-connected data holding elements (3), each data holding element (3) being connected to a data input line (5), each shift register (2), upon receiving an input control signal (INP) for the shift register (2), loading the data present on the data input lines (5) into the data holding elements (3) connected thereto; each shift register (2), upon receiving an output control signal (OUTP) for the shift register (2), outputting the datum buffer-stored in the last data holding element of the shift register (2), in which case there is connected downstream of each shift register (2) a further data holding element (10), which, upon receiving an input control signal (INP) for loading the preceding shift register (2), is preloaded with the datum for the first data holding element (3-3) of the shift register (2) and, upon reception of the output control signal (OUTP) for the shift register

Abstract: Latency time circuit for an S-DRAM, which is clocked by a high-frequency clock signal for producing a delayed data enable control signal for synchronous data transfer through a data path of the S-DRAM, having at least one controllable latency time generator for delaying a decoded data enable control signal with an adjustable latency time, characterized by at least one comparison circuit, which compares the cycle time of the high-frequency clock signal with a predetermined decoding time and by a signal delay circuit which can be switched on by means of the comparison circuit in order to delay the decoded data enable control signal with a predetermined delay time, in which the signal delay circuit is switched on by the comparison circuit when the cycle time of the clock signal is in a limit time region which is located about the predetermined decoding time.

Abstract: The circuit configuration has a memory array, a memory access controller, a control unit, and an input/output circuit. The control unit outputs a control signal simultaneously to the memory access controller and to the input/output circuit. When the control signal is received, the input/output circuit outputs data to the memory access controller via the data bus. When the control signal is received, the memory access controller stores the data present on the data bus in memory cells of the memory array. Owing to different geometric arrangements and different electrical capacitances, differences in propagation time of the control signals may occur on the path from the control unit to the memory access controller and from the control unit to the input/output circuit. For this purpose, a delay circuit or delay line is provided on the signal path to the memory access controller which brings about a delay of the control signal. This enables precise synchronization of the writing of data into the memory array.

Abstract: Control circuit for a data path of an S-DRAM which is clocked by a high-frequency clock signal, having a programmable mode register for storing a latency value; a latency generator for temporally delaying a data path control signal, generated by an internal sequence controller, with a switchable latency; a latency decoder, which switches the latency generator in a manner dependent on the latency value stored in the mode register, provision being made of at least one signal delay element, which can be switched in by the latency decoder and serves for the signal delay of the data path control signal with a specific delay time, the latency decoder switching in the associated signal delay element if the stored latency value is high.

Abstract: The invention relates to a DDR memory and to a storage method for storing data in a DDR memory having a plurality of memory cells which each have a prescribed word length, in which a serial data input is used to read in serial data on a rising or falling edge of the data clock signal, and a serial-parallel converter is used to put together a prescribed number of data items from the data read in to give a prescribed number of words from data words having the prescribed word length.

Abstract: The voltage pump for generating a boosted output voltage has a switch-on control circuit. The switch-on control includes a transistor that is connected between a terminal for feeding in a supply voltage and the terminal for tapping off the boosted output voltage. After the voltage pump has started to operate, the boosted output voltage is decoupled from the supply voltage by the transistor. A changeover switch forwards the respective higher of the output voltage or supply voltage to the substrate terminal and gate terminal of the transistor. The switch-on control enables early provision of a boosted output voltage in conjunction with reliable start-up operation of the voltage pump, while the additional outlay on circuitry is minimized.