Abstract: A semiconductor component includes a semiconductor layer (110) having a trench (326). The trench has first and second sides. A portion (713) of the semiconductor layer has a conductivity type and a charge density. The semiconductor component also includes a control electrode (540, 1240) in the trench. The semiconductor component further includes a channel region (120) in the semiconductor layer and adjacent to the trench. The semiconductor component still further includes a region (755) in the semiconductor layer. The region has a conductivity type different from that of the portion of the semiconductor layer. The region also has a charge density balancing the charge density of the portion of the semiconductor layer.

Abstract: A semiconductor component includes a semiconductor layer (110) having a trench (326). The trench has first and second sides. A portion (713) of the semiconductor layer has a conductivity type and a charge density. The semiconductor component also includes a control electrode (540, 1240) in the trench. The semiconductor component further includes a channel region (120) in the semiconductor layer and adjacent to the trench. The semiconductor component still further includes a region (755) in the semiconductor layer. The region has a conductivity type different from that of the portion of the semiconductor layer. The region also has a charge density balancing the charge density of the portion of the semiconductor layer.

Abstract: In one embodiment, a compound semiconductor vertical FET device (11) includes a first trench (29) formed in a body of semiconductor material (13), and a second trench (34) formed within the first trench (29) to define a channel region (61). A doped gate region (59) is then formed on the sidewalls and the bottom surface of the second trench (34). Source regions (26) are formed on opposite sides of the double trench structure (28). Localized gate contact regions (79) couple individual doped gate regions (59) together. Contacts (84,85,87) are then formed to the localized gate contact regions (79), the source regions (26), and an opposing surface (21) of the body of semiconductor material (13). The structure provides a compound semiconductor vertical FET device (11, 41, 711, 712, 811, 812) having enhanced blocking capability and improved switching performance.

Abstract: In one embodiment, a method for fabricating a compound semiconductor vertical FET device includes forming a first trench in a body of semiconductor material, and forming a self-aligned second trench within the first trench to define a channel region. A doped gate region is then formed on the sidewalls and the bottom surface of the second trench. Source regions are formed on opposite sides of the trench structure. Localized gate contact regions couple individual doped gate regions together. Contacts are then formed to the localized gate contact regions, the source regions, and an opposing surface of the body of semiconductor material. The method provides a compound semiconductor vertical FET structure having enhanced blocking capability.

Abstract: In one embodiment, a dc/dc converter network (71) is described. The converter network (71) includes at least one GaAs depletion mode or normally on FET device (711, 712). The converter network (71) is a two-port system having a positive input terminal (710), a positive output terminal (730), and a negative input terminal (720) connected to a negative output terminal (740). A first GaAs depletion mode FET (711) is connected between the positive input terminal (710) and an internal node (795). A second GaAs depletion mode FET (712) is connected between the internal node (795) and the common negative terminals (720, 740). A control circuit (780) is connected gate leads of the two FETs (711, 712), to alternatively switch the devices from a current conducting mode to a current blocking mode. An inductor (760) is connected between the internal node (795) and the positive output terminal (730). The GaAs depletion mode devices provide a converter network with improved performance.

Abstract: In one embodiment, a compound semiconductor vertical FET device (11) includes a first trench (29) formed in a body of semiconductor material (13), and a second trench (34) formed within the first trench (29) to define a channel region (61). A doped gate region (59) is then formed on the sidewalls and the bottom surface of the second trench (34). Source regions (26) are formed on opposite sides of the double trench structure (28). Localized gate contact regions (79) couple individual doped gate regions (59) together. Contacts (84,85,87) are then formed to the localized gate contact regions (79), the source regions (26), and an opposing surface (21) of the body of semiconductor material (13). The structure provides a compound semiconductor vertical FET device (11, 41, 711, 712, 811, 812) having enhanced blocking capability and improved switching performance.

Abstract: In one embodiment, a dc/dc converter network (71) is described. The converter network (71) includes at least one GaAs depletion mode or normally on FET device (711, 712). The converter network (71) is a two-port system having a positive input terminal (710), a positive output terminal (730), and a negative input terminal (720) connected to a negative output terminal (740). A first GaAs depletion mode FET (711) is connected between the positive input terminal (710) and an internal node (795). A second GaAs depletion mode FET (712) is connected between the internal node (795) and the common negative terminals (720, 740). A control circuit (780) is connected gate leads of the two FETs (711, 712), to alternatively switch the devices from a current conducting mode to a current blocking mode. An inductor (760) is connected between the internal node (795) and the positive output terminal (730). The GaAs depletion mode devices provide a converter network with improved performance.

Abstract: In one embodiment, a method for fabricating a compound semiconductor vertical FET device includes forming a first trench in a body of semiconductor material, and forming a self-aligned second trench within the first trench to define a channel region. A doped gate region is then formed on the sidewalls and the bottom surface of the second trench. Source regions are formed on opposite sides of the trench structure. Localized gate contact regions couple individual doped gate regions together. Contacts are then formed to the localized gate contact regions, the source regions, and an opposing surface of the body of semiconductor material. The method provides a compound semiconductor vertical FET structure having enhanced blocking capability.

Abstract: In one embodiment, a compound semiconductor vertical FET device (11) includes a first trench (29) formed in a body of semiconductor material (13), and a second trench (34) formed within the first trench (29) to define a channel region (61). A doped gate region (59) is then formed on the sidewalls and the bottom surface of the second trench (34). Source regions (26) are formed on opposite sides of the double trench structure (28). Localized gate contact regions (79) couple individual doped gate regions (59) together. Contacts (84, 85, 87) are then formed to the localized gate contact regions (79), the source regions (26), and an opposing surface (21) of the body of semiconductor material (13). The structure provides a compound semiconductor vertical FET device (11, 41, 711, 712, 811, 812) having enhanced blocking capability and improved switching performance.

Abstract: A semiconductor component includes a semiconductor layer (110) having a trench (326). The trench has first and second sides. A portion (713) of the semiconductor layer has a conductivity type and a charge density. The semiconductor component also includes a control electrode (540, 1240) in the trench. The semiconductor component further includes a channel region (120) in the semiconductor layer and adjacent to the trench. The semiconductor component still further includes a region (755) in the semiconductor layer. The region has a conductivity type different from that of the portion of the semiconductor layer. The region also has a charge density balancing the charge density of the portion of the semiconductor layer.

Abstract: A semiconductor component includes a semiconductor layer (110) having a trench (326). The trench has first and second sides. A portion (713) of the semiconductor layer has a conductivity type and a charge density. The semiconductor component also includes a control electrode (540, 1240) in the trench. The semiconductor component further includes a channel region (120) in the semiconductor layer and adjacent to the trench. The semiconductor component still further includes a region (755) in the semiconductor layer. The region has a conductivity type different from that of the portion of the semiconductor layer. The region also has a charge density balancing the charge density of the portion of the semiconductor layer.

Abstract: A semiconductor component includes a semiconductor layer (110) having a trench (326). The trench has first and second sides. A portion (713) of the semiconductor layer has a conductivity type and a charge density. The semiconductor component also includes a control electrode (540, 1240) in the trench. The semiconductor component further includes a channel region (120) in the semiconductor layer and adjacent to the trench. The semiconductor component still further includes a region (755) in the semiconductor layer. The region has a conductivity type different from that of the portion of the semiconductor layer. The region also has a charge density balancing the charge density of the portion of the semiconductor layer.

Abstract: An edge termination structure is created by forming trench structures (14) near a PN junction. The presence of the trench structures (14) extends a depletion region (13) between a doped region (12) and a body of semiconductor material or a semiconductor substrate (11) of the opposite conductivity type away from the doped region (12). This in turn forces junction breakdown to occur in the semiconductor bulk, leading to enhancement of the breakdown voltage of a semiconductor device (10). A surface of the trench structures (14) is covered with a conductive layer (16) which keeps the surface of the trench structures (14) at an equal voltage potential. This creates an equipotential surface across each of the trench structures (14) and forces the depletion region to extend laterally along the surface of semiconductor substrate (11).

Abstract: A semiconductor structure (10) uses a clamp (16) disposed at an edge (27) of a dielectric structure (14) in a semiconductor device. The clamp substantially reduces the separation or peeling of the dielectric structure or layer away from the underlying semiconductor material (20,24). The clamp also provides the benefit of protecting the interface between the dielectric layer and the underlying semiconductor material from chemical or moisture attack, either during later processing or after final manufacture. Such chemical or moisture attack and internal film stress are factors leading to separation of the dielectric film from the underlying semiconductor material. The clamp is useful, for example, in preventing separation of silicon nitride or oxide passivation from gallium arsenide substrates in power rectifier diodes.